Kevin,
What you need to do to take care of the busses and resources is walk
the PCIe configuration space to see if there is a SR-IOV configuration
space present. If there is then it should contain the data on offset
and stride it uses to allocate VFs. From that you can derive the
buses. As far as
Alex,
Okay, so it sounds like I need to cut into where coreboot detects what
PCI devices are present, sense whether they need buses and resources
allocated for SR-IOV, and then do so using whatever means coreboot is
already providing.
Is there a device-independent way to know whether and what
r
Hi Kevin,
The issue with the BIOS is that it is not assigning resources/buses
for SR-IOV. I'm not sure what tweaks would be needed in coreboot to
fix it.
The lspci -vvv you sent must be after the enabling the workarounds
since the buses/resources are populated. The reason why I was asking
for it
Hello!
I recently bought a ThinkPad T470 (6th gen i5-6300U) with an Intel Ethernet
I219-LM (rev 21). Installed fedora 28 and noticed a problem with link speed
after sleeping, it won't negotiate 1000Mbit/s after the machine went to
sleep once, staying at 10Mbit/s always and sometimes not passing an
