Never mind,
I've discover a bad interaction between the default ISR/VSR code and
the context switch code... that interrupt_end routine trying to switch
context while on an interrupt stack... That caused that the interrupt
controller code to clear the interrupt priority (for the clok, the
only one
Hi there,
Testing my hal for Cortex-R4, I'm getting a funny behaviour for test
kernel/.../thread2. It seems that when two threads have the same
priority, there is no timeslicing working (interestingly, the
timeslice tests also get deadlocked).
The problem seems to appear because thread#2 preem
