It makes sense now. Thanks, Nagaraj
Nick Garnett writes:
> "Christophe Coutand" writes:
>
> > My understanding is:
> >
> > CYGNUM_HAL_CORTEXM_PRIORITY_MAX is defined equal to
> > 1<<(8-CYGNUM_HAL_CORTEXM_PRIORITY_LEVEL_BITS)
> >
> > What the eCos implementation really does is to reserved level 0 for
> > DEBUG and SVC traps. If
"Christophe Coutand" writes:
> My understanding is:
>
> CYGNUM_HAL_CORTEXM_PRIORITY_MAX is defined equal to
> 1<<(8-CYGNUM_HAL_CORTEXM_PRIORITY_LEVEL_BITS)
>
> What the eCos implementation really does is to reserved level 0 for
> DEBUG and SVC traps. If you call hal_interrupt_set_level with lev
M3 HAL interrupt-priority code bug
Nagaraj K writes:
> I see that this function wrongly implements the priority level in
> Cortex-M3 processor. According to the Cortex-M3 data sheet, we need to
> write the priority level to the top N bits of the register where N is
> the number of p
Nagaraj K writes:
> I see that this function wrongly implements the priority level in
> Cortex-M3 processor. According to the Cortex-M3 data sheet, we need to
> write the priority level to the top N bits of the register where N is
> the number of priority level bits implemented in this particular
Hi,
I was browsing through the Cortex-M3 HAL port and everything looks
OK except for the function
hal_interrupt_set_level() in hal\cortexm\arch\current\src\hal_misc.c
Here is the original function.
__externC void hal_interrupt_set_level( cyg_uint32 vector, cyg_uint32 level )
{
cyg_uint32 l
