Nil UUID is a special case with all zeros value. This
patch is to handle this case to avoid the invalid DUID.
Cc: Naveen Santhapur
Cc: Ye Ting
Cc: Fu Siyuan
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Wu
Reviewed-by: Ye Ting
-Original Message-
From: Wu, Jiaxin
Sent: Tuesday, February 28, 2017 3:08 PM
To: edk2-devel@lists.01.org
Cc: Ye, Ting ; Fu, Siyuan ; Wu, Jiaxin
Subject: [Patch]
Reviewed-by: Jeff Fan
-Original Message-
From: Leo Duran [mailto:leo.du...@amd.com]
Sent: Friday, March 03, 2017 7:36 AM
To: edk2-de...@ml01.01.org
Cc: Leo Duran; Fan, Jeff; Tian, Feng; Zeng, Star; Laszlo Ersek; Brijesh Singh
Subject: [PATCH] UefiCpuPkg/CpuDxe: Add
Ard,
The code line below also needs to be considered.
if (RemainingPages < Pages) {
The Pages needs to be converted to granularity aligned before the if statement,
like the code below in DXE phase.
NumberOfPages += EFI_SIZE_TO_PAGES (Alignment) - 1;
NumberOfPages &= ~(EFI_SIZE_TO_PAGES
Add comments for functions.
Cc: Ard Biesheuvel
Cc: Star Zeng
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Dandan Bi
---
MdeModulePkg/Core/Dxe/Mem/Pool.c | 19 +++
Cc: Brijesh Singh
Cc: Leo Duran
Cc: Ard Biesheuvel
Cc: Star Zeng
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Dandan Bi
---
MdeModulePkg/MdeModulePkg.dec |
Leo,
I talked with Jiewen in office today. He felt that Intel might have a similar
need of such layer of abstraction (BmDmaLib).
We are investigating it. Can you please wait for several days?
We'd like to review the current interfaces of BmDmaLib to make sure it's
general enough to meet any
Hi,
On 02/24/2017 11:08 AM, Ard Biesheuvel wrote:
On 23 February 2017 at 22:33, Jeremy Linton wrote:
Create a new module that adds the callbacks to support
the EFI SCSI pass-through protocol. These callbacks
wrap around the existing ATA pass-through callbacks.
In
This PCD holds the address mask for page table entries when memory
encryption is enabled on AMD processors supporting the Secure Encrypted
Virtualization (SEV) feature.
The mask is applied when page tables entries are created or modified.
CC: Jeff Fan
Cc: Feng Tian
This PCD holds the address mask for page table entries when memory
encryption is enabled on AMD processors supporting the Secure Encrypted
Virtualization (SEV) feature.
The mask is applied when page tables entries are created or modified.
This patch follows [PATCH v4 0/6] Add PCD
On 03/02/17 18:22, Ard Biesheuvel wrote:
> On 2 March 2017 at 17:09, Laszlo Ersek wrote:
>> On 03/02/17 17:15, Ard Biesheuvel wrote:
>>> This wires up the existing basic support for capsules left in memory by
>>> the OS across a warm reset. This involves wiring up the PEI phase
This series provides an abstraction layer for Bus-master DMA operations as
currently implemented by the PciHostBridgeDxe driver. The intent is to then
allow override of this library as may be required by specific hardware
implementations, such as AMD's Secure Encrypted Virtualization (SEV).
This patch provides an abstraction layer for Bus-master DMA operations as
currently implemented by the PciHostBridgeDxe driver. The intent is to then
allow override of this library as may be required by specific hardware
implementations, such as AMD's Secure Encrypted Virtualization (SEV).
This
This patch adds the new DxeBmDmaLib (BmDmaLib class) library, which
provides an abstraction layer for DMA operations implemented by the
PciHostBridgeDxe driver.
Cc: Jordan Justen
Cc: Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement
The BmDmaLib class library provides an abstraction layer for Bus-master DMA
operations as currently implemented by the PciHostBridgeDxe driver. The
intent is to allow override of the library as required by specific hardware
implementations, such as AMD's Secure Encrypted Virtualization (SEV).
Cc:
This patch adds the new DxeBmDmaLib (BmDmaLib class) library, which
provides an abstraction layer for DMA operations implemented by the
PciHostBridgeDxe driver.
Cc: Feng Tian
Cc: Star Zeng
Contributed-under: TianoCore Contribution Agreement 1.0
This patch adds the new DxeBmDmaLib (BmDmaLib class) library, which
provides an abstraction layer for DMA operations implemented by the
PciHostBridgeDxe driver.
Cc: Laszlo Ersek
Cc: Ard Biesheuvel
Contributed-under: TianoCore Contribution Agreement
This patch adds the new DxeBmDmaLib (BmDmaLib class) library, which
provides an abstraction layer for DMA operations implemented by the
PciHostBridgeDxe driver.
Cc: Maurice Ma
Cc: Prince Agyeman
Contributed-under: TianoCore Contribution Agreement
For UEFI Drivers/Applications there is also the EFI_TIMESTAMP_PROTOCOL
if it is available on your platform.
Mike
> -Original Message-
> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of Michael
> Zimmermann
> Sent: Thursday, March 2, 2017 4:06 AM
> To: Arka Sharma
On 2 March 2017 at 17:09, Laszlo Ersek wrote:
> On 03/02/17 17:15, Ard Biesheuvel wrote:
>> This wires up the existing basic support for capsules left in memory by
>> the OS across a warm reset. This involves wiring up the PEI phase modules
>> to preserve the capsule images
On 03/02/17 17:15, Ard Biesheuvel wrote:
> This wires up the existing basic support for capsules left in memory by
> the OS across a warm reset. This involves wiring up the PEI phase modules
> to preserve the capsule images before releasing the memory for normal
> consumption, and some tweaks to
This wires up the existing code for processing capsule: it enables
CapsulePei, which preserves capsules left in memory by the OS, and
combined with the PlatformBootManagerLib and other changes in previous
patches, this will ensure that capsules are handed back to the OS
via the system table if it
Look for any capsules left in memory by the OS across reset before
releasing the memory for normal use, so that they can be preserved and
processed later.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel
---
Instead of unconditionally returning BOOT_WITH_FULL_CONFIGURATION when
enquiring the platform about the boot mode, let's return enable the use
of capsules by returning BOOT_ON_FLASH_UPDATE when a capsule HOB is
detected.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard
Process any capsule HOBs that were left for us by CapsulePei. This
involves calling ProcessCapsules() twice, as explained in the comment
in DxeCapsuleLibFmp.
1) The first call must be before EndOfDxe. The system capsules is processed.
If device capsule FMP protocols are exposted at this time
This wires up the existing basic support for capsules left in memory by
the OS across a warm reset. This involves wiring up the PEI phase modules
to preserve the capsule images before releasing the memory for normal
consumption, and some tweaks to the boot mode and BDS platform routines.
As
Architectures such as AArch64 may run the OS with 16 KB or 64 KB sized
pages, and for this reason, the UEFI spec mandates a minimal allocation
granularity of 64 KB for regions that may require different memory
attributes at OS runtime.
So make PeiCore's implementation of AllocatePages () take
AFAIK the only way to do that is to use the platform specific TimerLib
like this:
UINT64
GetTimeMs (
VOID
)
{
return GetTimeInNanoSecond(GetPerformanceCounter()) / 100ULL;
}
Thanks
Michael
On Thu, Mar 2, 2017 at 12:53 PM, Arka Sharma wrote:
> gRT->GetTime() is
gRT->GetTime() is accurate about seconds.Is there any way to calculate
time difference in milliseconds ?
Let's say
Time1 = GetTimeMs();
//
// Some tasks
//
Time2 = GetTimeMs();
//
// Time taken
//
GetTimeDiff (Time1, Time2);
Something like this
Regards,
Arka
Like for AARCH64, enable PE/COFF image and NX memory protection for all
32-bit ARM virt platforms.
Note that this does not [yet] protect EfiLoaderData regions, due to
compatibility issues with GRUB.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel
Enable the use of strict memory permissions on ARM by processing the
EFI_MEMORY_RO and EFI_MEMORY_XP rather than ignoring them. As before,
calls to CpuArchProtocol::SetMemoryAttributes that only set RO/XP
bits will preserve the cacheability attributes. Permissions attributes
are not preserved when
Currently, any range passed to CpuArchProtocol::SetMemoryAttributes is
fully broken down into page mappings if the start or the size of the
region happens to be misaliged relative to the section size of 1 MB.
This is going to hurt when we enable strict memory permissions, given
that we remap the
Page and section entries in the page tables are updated using the
helper ArmUpdateTranslationTableEntry(), which cleans the page
table entry to the PoC, and invalidates the TLB entry covering
the page described by the entry being updated.
Since we may be updating section entries, we might be
This series makes the prerequisite modifications to the ARM version of
the CpuDxe driver so we can enable PE/COFF image and NX memory protection
for ARM platforms, including ArmVirtPkg (#4)
Patch #1 refactors CpuSetMemoryAttributes() so it no longer splits section
mappings into page mappings
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