This patch updates PxeBcIcmpErrorDpcHandle() and PxeBcIcmp6ErrorDpcHandle() to
recycle the ICMP packet after copy it to PXE mode data.
Cc: Ye Ting
Cc: Wu Jiaxin
Cc: Wang Fan
Contributed-under: TianoCore Contribution Agreement 1.0
Hi, Jiaxin
In the line you are modifying the UDNI is always not started. You should move
the Nii->Id to the line after PxeStart(), not to check it here.
BestRegards
Fu Siyuan
> -Original Message-
> From: Wu, Jiaxin
> Sent: Thursday, December 21, 2017 3:13 PM
> To:
Reviewed-by: Ye Ting
-Original Message-
From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of Fu,
Siyuan
Sent: Wednesday, December 13, 2017 10:16 AM
To: edk2-devel@lists.01.org
Cc: Ye, Ting ; Wang, Fan ; Wu,
Another, please also more comments for the fields in
NV_STORE_DEFAULT_BUFFER_HEADER.
Thanks,
Star
-Original Message-
From: Zeng, Star
Sent: Thursday, December 21, 2017 3:11 PM
To: Gao, Liming ; edk2-devel@lists.01.org
Cc: Zhu, Yonghong ;
Liming,
I have some comments to the patch series about MdeModulePkg changes.
For MdeModulePkg: Update PCD driver to support Dynamic PcdVpdBaseAddress,
Could the if condition adjustment be removed? And how about declaring "extern
UINT32 mVpdBaseAddress;" in Service.h instead of Service.c?
For
In HttpBootCallback(), when data type is HttpBootHttpResponse, function may meet
the resource redirect error. In current implementation, function will still go
ahead to find header for HTTP_HEADER_CONTENT_LENGTH, this is not expected.
Function
should break in redirect status error handling.
Cc:
Cc: Wang Fan
Cc: Ye Ting
Cc: Fu Siyuan
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Wu Jiaxin
Jiaxin Wu (2):
NetworkPkg/HttpBootDxe: Avoid the potential memory leak when eror
Thanks. .uni file will be updated accordingly.
Regards,
Jian
> -Original Message-
> From: Zeng, Star
> Sent: Thursday, December 21, 2017 1:15 PM
> To: Wang, Jian J ; edk2-devel@lists.01.org
> Cc: Dong, Eric ; Zeng, Star
>
Cc: Ye Ting
Cc: Long Qin
Cc: Fu Siyuan
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Wu Jiaxin
---
CryptoPkg/Include/Library/TlsLib.h | 6 ++
CryptoPkg/Library/TlsLib/TlsConfig.c |
Please also the *.uni file accordingly, with that, Reviewed-by: Star Zeng
Thanks,
Star
-Original Message-
From: Wang, Jian J
Sent: Thursday, December 21, 2017 1:08 PM
To: edk2-devel@lists.01.org
Cc: Zeng, Star ; Dong, Eric
Your requirement doesn't need any PCD knowledge.
I think all you need to do:
1. Study to know how to embedded a binary to your PE image
a). Either by converting that binary to a big C array
b). Or by creating a new resource section, including that binary
2. In your entrypoint of the
The first 48 bytes contain the microcode update header.
DataSize must be a multiple of DWORDs.
TotalSize is always a multiple of 1024.
Both size of CPU_MICROCODE_EXTENDED_TABLE_HEADER and
CPU_MICROCODE_EXTENDED_TABLE are multiple of DWORDs.
So (ExtendedTableLength & 0x3)!=0 should be
On 20 December 2017 at 19:28, M1cha wrote:
> From what I can see this bug dates back to the commit from 2011 where
> support for this was added: 2cf4b60895f8a
>
> The first problem is that PopulateLevel2PageTable overflows the
> translation table buffer because it
On 19 December 2017 at 08:57, M1cha wrote:
> From what I can see this bug dates back to the commit from 2011 where
> support for this was added: 2cf4b60895f8a
>
> The first problem is that PopulateLevel2PageTable overflows the
> translation table buffer because it
On 20 December 2017 at 15:17, gary guo wrote:
> On Wed, Dec 20, 2017 at 09:13:58AM +, Ard Biesheuvel wrote:
>> Hi Heyi,
>>
>> On 20 December 2017 at 08:21, Heyi Guo wrote:
>> > PCIe on some ARM platforms requires address translation, not only for
>>
On 20 December 2017 at 15:17, Alexei Fedorov wrote:
> Hi Ard,
>
>
> The side effect of the following commit on 6 April:
>
>
> ArmPlatformPkg/FVP: map motherboard VRAM as uncached memory
>
> The VRAM of the PL111 on the FVP Base/Foundation models is described as
> device
Hi Ard,
The side effect of the following commit on 6 April:
ArmPlatformPkg/FVP: map motherboard VRAM as uncached memory
The VRAM of the PL111 on the FVP Base/Foundation models is described as
device memory rather than uncached memory, which is not an accurate
description of the nature of the
Change BIOS Minor Version
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: lushifex
---
Platform/BroxtonPlatformPkg/BiosId.env | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Platform/BroxtonPlatformPkg/BiosId.env
Change binaries from Common folder to Board folder.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: lushifex
---
Platform/BroxtonPlatformPkg/BuildBxtBios.sh| 56 +++---
.../Common/Tools/Stitch/IFWIStitch_Simple.bat | 36
PCIe on some ARM platforms requires address translation, not only for
legacy IO access, but also for 32bit memory BAR access as well. There
will be "Address Translation Unit" or something similar in PCI host
bridges to translation CPU address to PCI address and vice versa. So
we think it may be
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