Sure. A little busy these days; I'll do that ASAP.
Thanks,
Heyi
On Thu, Jun 07, 2018 at 01:11:59PM +0200, Ard Biesheuvel wrote:
> On 17 April 2018 at 03:20, Guo Heyi wrote:
> > Hi Ard,
> >
> > I tested mm -io on D05, for root bridge 4 with CPU IO address starting from
> > 0x8_abff, and it w
gt;
> > > > > > >
> > > > > > > On Thu, Dec 21, 2017 at 08:32:37AM +, Ard Biesheuvel wrote:
> > > > > > > >
> > > > > > > >
> > > > > > > > On 21 December 2017 at 08:27, G
On Wed, Dec 20, 2017 at 09:13:58AM +, Ard Biesheuvel wrote:
> Hi Heyi,
>
> On 20 December 2017 at 08:21, Heyi Guo wrote:
> > PCIe on some ARM platforms requires address translation, not only for
> > legacy IO access, but also for 32bit memory BAR access as well. There
> > will be "Address Tra
3 matches
Mail list logo