(1) SmmRelocationSemaphoreComplete32() runs in 32-bit mode, so wrap it in
a (BITS 32 ... BITS 64) bracket.
(2) SmmRelocationSemaphoreComplete32() currently compiles to:
> 000002AE C6050000000001 mov byte [dword 0x0],0x1
> 000002B5 FF2500000000 jmp dword [dword 0x0]
where the first instruction is patched with the contents of
"mRebasedFlag" (so that (*mRebasedFlag) is set to 1), and the second
instruction is patched with the address of
"mSmmRelocationOriginalAddress" (so that we jump to
"mSmmRelocationOriginalAddress").
In its current form the first instruction could not be patched with
PatchInstructionX86(), given that the operand to patch is not encoded
in the trailing bytes of the instruction. Therefore, adopt an
EAX-based version, inspired by both the IA32 and X64 variants of
SmmRelocationSemaphoreComplete():
> 000002AE 50 push eax
> 000002AF B800000000 mov eax,0x0
> 000002B4 C60001 mov byte [eax],0x1
> 000002B7 58 pop eax
> 000002B8 FF2500000000 jmp dword [dword 0x0]
Here both instructions can be patched with PatchInstructionX86(), and
the DBs can be replaced with native NASM syntax.
(3) Turn the "mRebasedFlagAddr32" and "mSmmRelocationOriginalAddressPtr32"
variables into markers that suit PatchInstructionX86().
This removes the last instructions encoded with DBs from PiSmmCpuDxeSmm.
Cc: Eric Dong <eric.d...@intel.com>
Cc: Jiewen Yao <jiewen....@intel.com>
Cc: Liming Gao <liming....@intel.com>
Cc: Michael D Kinney <michael.d.kin...@intel.com>
Cc: Ruiyu Ni <ruiyu...@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=866
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Laszlo Ersek <ler...@redhat.com>
---
UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c | 16 +++++++++----
UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm | 24 +++++++++-----------
2 files changed, 23 insertions(+), 17 deletions(-)
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c
b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c
index 6dbcb086aa4d..1586bbb626bb 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c
@@ -15,8 +15,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
EXPRESS OR IMPLIED.
#include "PiSmmCpuDxeSmm.h"
-extern UINT32 mSmmRelocationOriginalAddressPtr32;
-extern UINT32 mRebasedFlagAddr32;
+extern UINT8 gPatchSmmRelocationOriginalAddressPtr32;
+extern UINT8 gPatchRebasedFlagAddr32;
UINTN mSmmRelocationOriginalAddress;
volatile BOOLEAN *mRebasedFlag;
@@ -49,7 +49,11 @@ SemaphoreHook (
UINTN TempValue;
mRebasedFlag = RebasedFlag;
- mRebasedFlagAddr32 = (UINT32)(UINTN)mRebasedFlag;
+ PatchInstructionX86 (
+ &gPatchRebasedFlagAddr32,
+ (UINT32)(UINTN)mRebasedFlag,
+ 4
+ );
CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE +
SMRAM_SAVE_STATE_MAP_OFFSET);
mSmmRelocationOriginalAddress = HookReturnFromSmm (
@@ -63,5 +67,9 @@ SemaphoreHook (
// Use temp value to fix ICC complier warning
//
TempValue = (UINTN)&mSmmRelocationOriginalAddress;
- mSmmRelocationOriginalAddressPtr32 = (UINT32)TempValue;
+ PatchInstructionX86 (
+ &gPatchSmmRelocationOriginalAddressPtr32,
+ (UINT32)TempValue,
+ 4
+ );
}
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
index eae14c0549f0..0b0c3f28e53f 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
@@ -29,8 +29,8 @@ global ASM_PFX(gPatchSmmInitStack)
global ASM_PFX(gcSmiInitGdtr)
global ASM_PFX(gcSmmInitSize)
global ASM_PFX(gcSmmInitTemplate)
-global ASM_PFX(mRebasedFlagAddr32)
-global ASM_PFX(mSmmRelocationOriginalAddressPtr32)
+global ASM_PFX(gPatchRebasedFlagAddr32)
+global ASM_PFX(gPatchSmmRelocationOriginalAddressPtr32)
%define LONG_MODE_CS 0x38
@@ -125,20 +125,18 @@ ASM_PFX(SmmRelocationSemaphoreComplete):
;
; Semaphore code running in 32-bit mode
;
+BITS 32
global ASM_PFX(SmmRelocationSemaphoreComplete32)
ASM_PFX(SmmRelocationSemaphoreComplete32):
- ;
- ; mov byte ptr [], 1
- ;
- db 0xc6, 0x5
-ASM_PFX(mRebasedFlagAddr32): dd 0
- db 1
- ;
- ; jmp dword ptr []
- ;
- db 0xff, 0x25
-ASM_PFX(mSmmRelocationOriginalAddressPtr32): dd 0
+ push eax
+ mov eax, strict dword 0 ; source operand will be patched
+ASM_PFX(gPatchRebasedFlagAddr32):
+ mov byte [eax], 1
+ pop eax
+ jmp dword [dword 0] ; destination will be patched
+ASM_PFX(gPatchSmmRelocationOriginalAddressPtr32):
+BITS 64
global ASM_PFX(PiSmmCpuSmmInitFixupAddress)
ASM_PFX(PiSmmCpuSmmInitFixupAddress):
lea rax, [@LongMode]
--
2.14.1.3.gb7cf6e02401b
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