Yes. I agree.
It is a good idea to add comment to clarify the mismatch.
Again, thanks to catch that.
Thank you
Yao Jiewen
From: Mudusuru, Giri P
Sent: Wednesday, June 1, 2016 1:31 PM
To: Yao, Jiewen ; edk2-devel@lists.01.org
Cc: Mudusuru, Giri P
Subject: RE: [PATCH 2/2] IntelSiliconPkg/IgdOpReg
Thanks Jiewen for clarification. Can you please add comments in file to avoid
confusion during check-in?
Reviewed-by: Giri P Mudusuru
Thanks,
-Giri
-Original Message-
From: Yao, Jiewen
Sent: Tuesday, May 31, 2016 10:26 PM
To: Mudusuru, Giri P ; edk2-devel@lists.01.org
Subject: RE: [PAT
HI Giri
Thanks! I did check spec. Comments below:
1) I think it is a spec bug. The size should be 0xA0 if we want to make sure
the OPREGION_HEADER is 0x100 bytes. (0xA0 + 96 = 0x100). So I fixed it when I
write the code.
2) I think it is a spec bug The size should be 0x3C if we want to make sur
Thanks Jiewen. Few comments.
1) Size of RSV1 in OPREGION HEADER as per spec is 0x9F and in code it is 0x3C
(table2-2 section 2.2.1)
+ UINT8 RSV1[0xA0]; ///< Offset 96 Reserved
+} INTEL_IGD_OPREGION_HEADER;
2) Size of RSV3 in MBOX1 as per spec is 0x40 and in code it is 0x3C (table3-1
secti
Add IGD OpRegion definition from Intel Integrated Graphics Device OpRegion
Specification.
at https://01.org/sites/default/files/documentation/acpi_igd_opregion_spec_0.pdf
Cc: Giri P Mudusuru
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao
---
IntelSiliconPkg/In
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