On 31 January 2017 at 11:44, Leif Lindholm wrote:
> On Tue, Jan 31, 2017 at 09:48:11AM +, Ryan Harkin wrote:
>> On 26 January 2017 at 14:36, Leif Lindholm wrote:
>> > On Fri, Jan 20, 2017 at 05:10:45PM +0530, Bhupesh Sharma wrote:
>> >> ARM TZASC-380 IP provides a mechanism to split memory re
On Tue, Jan 31, 2017 at 09:48:11AM +, Ryan Harkin wrote:
> On 26 January 2017 at 14:36, Leif Lindholm wrote:
> > On Fri, Jan 20, 2017 at 05:10:45PM +0530, Bhupesh Sharma wrote:
> >> ARM TZASC-380 IP provides a mechanism to split memory regions being
> >> protected via it into eight equal-sized
On 26 January 2017 at 14:36, Leif Lindholm wrote:
> On Fri, Jan 20, 2017 at 05:10:45PM +0530, Bhupesh Sharma wrote:
>> ARM TZASC-380 IP provides a mechanism to split memory regions being
>> protected via it into eight equal-sized sub-regions. A bit-setting
>> allows the corresponding subregion to
On Thu, Jan 26, 2017 at 8:06 PM, Leif Lindholm wrote:
> On Fri, Jan 20, 2017 at 05:10:45PM +0530, Bhupesh Sharma wrote:
>> ARM TZASC-380 IP provides a mechanism to split memory regions being
>> protected via it into eight equal-sized sub-regions. A bit-setting
>> allows the corresponding subregion
On Fri, Jan 20, 2017 at 05:10:45PM +0530, Bhupesh Sharma wrote:
> ARM TZASC-380 IP provides a mechanism to split memory regions being
> protected via it into eight equal-sized sub-regions. A bit-setting
> allows the corresponding subregion to be disabled.
>
> Several NXP/FSL SoCs support the TZASC
ARM TZASC-380 IP provides a mechanism to split memory regions being
protected via it into eight equal-sized sub-regions. A bit-setting
allows the corresponding subregion to be disabled.
Several NXP/FSL SoCs support the TZASC-380 IP block and allow
the DDR connected via the TZASC to be partitioned
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