On Fri, Feb 23, 2018 at 09:02:46AM +, Ard Biesheuvel wrote:
> On 23 February 2018 at 03:17, Guo Heyi wrote:
> > Hi Jeremy,
> >
> > This TF binaries have not been patched the latest SMCCC workaround; it is
> > based
> > on v1.4 release and was only
> > patched with "disable/enable MMU in PSCI
On 23 February 2018 at 03:17, Guo Heyi wrote:
> Hi Jeremy,
>
> This TF binaries have not been patched the latest SMCCC workaround; it is
> based
> on v1.4 release and was only
> patched with "disable/enable MMU in PSCI SMC call", as the commit in upstream
> TF
> code:
> f62ad322695d16178db464dc0
Hi Jeremy,
This TF binaries have not been patched the latest SMCCC workaround; it is based
on v1.4 release and was only
patched with "disable/enable MMU in PSCI SMC call", as the commit in upstream TF
code:
f62ad322695d16178db464dc062fe0af592c6780
When we generated these binaries, SMCCC patches
Hi,
On 02/02/2018 05:57 AM, Heyi Guo wrote:
1 Workarounds for CVE-2017-5715 on Cortex A57/A72/A73 and A75 #1214.
I've been trying to verify spectre fixes, and I don't get a smccc
version from this firmware (see this kernel branch
https://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.gi
1 Workarounds for CVE-2017-5715 on Cortex A57/A72/A73 and A75 #1214.
2 Upgrade trusted firmware to 1.4
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
Signed-off-by: Heyi Guo
Reviewed-by: Leif Lindholm
Reviewed-by: Ard Biesheuvel
---
Platform/Hisilicon/D05/bl
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