On Tue, 2016-03-08 at 15:20 +0100, Laszlo Ersek wrote:
> +UINT64 PciExBarBase;
...
> if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
...
> + PciExBarBase = FixedPcdGet64 (PcdPciExpressBaseAddress);
...
> }
...
> if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
...
> +
On 03/18/16 15:38, David Woodhouse wrote:
> On Tue, 2016-03-08 at 15:20 +0100, Laszlo Ersek wrote:
>> +UINT64 PciExBarBase;
> ...
>> if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
> ...
>> + PciExBarBase = FixedPcdGet64 (PcdPciExpressBaseAddress);
> ...
>> }
> ...
>> if
The comments in the code should speak for themselves; here we note only
two facts:
- The PCI config space writes (to the PCIEXBAR register) are performed
using the 0xCF8 / 0xCFC IO ports, by virtue of PciLib being resolved to
BasePciLibCf8. (This library resolution will permanently remain in p
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