On Tue, 4 Dec 2018 at 18:19, Leif Lindholm wrote:
>
> On Tue, Dec 04, 2018 at 05:40:14PM +0100, Ard Biesheuvel wrote:
> > > > +STATIC
> > > > +EFI_STATUS
> > > > +MvGpioGetValue (
> > > > + IN MARVELL_GPIO_PROTOCOL *This,
> > > > + IN UINTN ControllerIndex,
> > > > + IN UINTN GpioPi
On Tue, Dec 04, 2018 at 05:40:14PM +0100, Ard Biesheuvel wrote:
> > > +STATIC
> > > +EFI_STATUS
> > > +MvGpioGetValue (
> > > + IN MARVELL_GPIO_PROTOCOL *This,
> > > + IN UINTN ControllerIndex,
> > > + IN UINTN GpioPin,
> > > + IN OUT BOOLEAN *Value
> > > + )
> > > +{
> > > + UINT
On Tue, 4 Dec 2018 at 17:37, Leif Lindholm wrote:
>
> On Sat, Oct 20, 2018 at 03:57:37AM +0200, Marcin Wojtas wrote:
> > From: jinghua
> >
> > Marvell Armada 7k/8k SoCs comprise integrated GPIO controllers,
> > one in AP and two in each possible CP hardware blocks.
> >
> > This patch introduces s
On Sat, Oct 20, 2018 at 03:57:37AM +0200, Marcin Wojtas wrote:
> From: jinghua
>
> Marvell Armada 7k/8k SoCs comprise integrated GPIO controllers,
> one in AP and two in each possible CP hardware blocks.
>
> This patch introduces support for them, which is a producer of
> MARVELL_GPIO_PROTOCOL,
From: jinghua
Marvell Armada 7k/8k SoCs comprise integrated GPIO controllers,
one in AP and two in each possible CP hardware blocks.
This patch introduces support for them, which is a producer of
MARVELL_GPIO_PROTOCOL, which add necessary routines.
Hardware description of the controllers is plac
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