On 2015-04-22 01:25:42, Jeff Fan wrote:
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Jeff Fan
> ---
> .../Library/DebugAgent/DebugAgentCommon/DebugAgent.c | 19
> +--
> 1 file changed, 17 insertions(+), 2 deletions(-)
>
> diff --git
> a/SourceLeve
Laszlo,
Thanks for your detailed educations:)
For your suggestion (6), can you check this url
(https://github.com/niruiyu/edk2/compare/master...niruiyu:new_bds)? Is this
what you want me to do?
What I did is to firstly fork a edk2 in my personal git repository and then
clone that to my local mac
So I'm using AHCI register to send commands to a ATA device.
I can access the returned 512 Buffer but I don't know yet how to read the
Received D2H FIS or Received PIO FIS.
I implement the structures showed here:
http://wiki.osdev.org/AHCI
I've tested the AtaPassThruProtocol too and used Asb
On 04/24/15 16:50, Yao, Jiewen wrote:
> Hi Laszlo
>
> I think there is good resource for your reference - Intel Quark.
> https://downloadcenter.intel.com/download/23197
>
> You may download "Board_Support_Package_Sources_for_Intel_Quark_v1.1.0.7z",
> and find "Quark_EDKII_v1.1.0"
>
> IA32Family
Reviewed-by: Michael Kinney
-Original Message-
From: Gao, Liming
Sent: Friday, April 24, 2015 1:15 AM
To: Wu, Hao A; Kinney, Michael D
Cc: edk2-devel@lists.sourceforge.net
Subject: RE: [PATCH] IntelFrameworkModulePkg: Modify IsaSerialDxe to follow
driver rules
Reviewed-by: Liming Gao
> I'm using AtaPassThru to issue command B0/DA :
correcting
command B0/D4
(B0/48 is to enable Smart)
--
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Hi everyone.
I have more a obstacle.
I'm using AtaPassThru to issue command B0/DA :
//--
Packet.Protocol =
EFI_ATA_PASS_THRU_PROTOCOL_ATA_NON_DATA;
Packet.Length =
EFI
Hi Laszlo
I think there is good resource for your reference - Intel Quark.
https://downloadcenter.intel.com/download/23197
You may download "Board_Support_Package_Sources_for_Intel_Quark_v1.1.0.7z", and
find "Quark_EDKII_v1.1.0"
IA32FamilyCpuBasePkg\PiSmmCpuDxeSmm - it is CPUSMM driver.
IA32Fam
Got it. Thanks!
-Original Message-
From: Paolo Bonzini [mailto:pbonz...@redhat.com]
Sent: Friday, April 24, 2015 9:01 PM
To: Yao, Jiewen; edk2-devel@lists.sourceforge.net; Gerd Hoffmann
Cc: qemu-de...@nongnu.org; m...@redhat.com
Subject: Re: [edk2] implementing EFI_SMM_CONTROL2_PROTOCOL.T
On 24/04/2015 13:56, Yao, Jiewen wrote:
> BTW: I am not sure how QEMU emulate SMI. Does SMI can be trigger by
> 0xB2 port? And CPU will run to SMBASE in real mode?
Yes, operation is the same.
Paolo
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One dashboard for
Hi Laszlo
Below is my thought.
2) You are right. According to IA32 manual - "Maskable hardware interrupts,
exceptions, NMI interrupts, SMI interrupts, A20M interrupts, single-step traps,
breakpoint traps, and INIT operations are inhibited when the processor enters
SMM." You can also find more d
Thanks, Devkate.
To follow EDKII open forum review process, I add the patch below to see if
others have comments.
Subject: [PATCH] MdeModulePkg/NvmExpressDxe: Correct Prp list creation
algorithm.
Fix the algo of Prp list creation to calculate the number of Prp lists and the
number of entries i
Reviewed-by: Ye Ting mailto:ting...@intel.com>>
From: Fu Siyuan [mailto:siyuan...@intel.com]
Sent: Friday, April 24, 2015 11:37 AM
To: edk2-devel@lists.sourceforge.net
Subject: [edk2] [Patch] NetworkPkg: Remove duplicate DAD entry in IP6 driver to
fix DAD fail issue.
---
Reviewed-by: Liming Gao
-Original Message-
From: Wu, Hao A
Sent: Friday, April 24, 2015 4:15 PM
To: Gao, Liming; Kinney, Michael D
Cc: edk2-devel@lists.sourceforge.net
Subject: [PATCH] IntelFrameworkModulePkg: Modify IsaSerialDxe to follow driver
rules
IsaSerialDxe creates child handle
IsaSerialDxe creates child handles and wishes to retrieve the name for
those child controllers.
However, in the IsaSerialComponentNameGetControllerName() function, it
directly return EFI_UNSUPPORTED when ChildHandle != NULL.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ha
Hi Jaben,
The run time service 'QueryVariableInfo' is not proper to be used to get the
variable name size. This patch refine the logic about allocating memory for
variable name and data.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Qiu Shumin mailto:shumin@intel.com
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