Hi again Feng,
After a more careful examination, there is a problem with your latest patch.
When FIS is received and D2H is not received, Status remains set to
EFI_ERROR, due to the D2H check which comes after the FIS check.
Cheers,
A. Sava
On Tue, Sep 2, 2014 at 3:30 PM, Reza Jelveh wrote
ed to
check the TFD after receiving a SetupFIS.
Reviewed-by: A. Sava
On Tue, Sep 2, 2014 at 8:21 AM, Tian, Feng wrote:
> Hi, Sava
>
>
>
> From my side, I am ok with integrating these two cases into one.
>
>
>
> Please help review and verify if the attached patch is
As we add now Ahci support, we probably should also add Ahci support to Csm
module (IntelFrameworkModulePkg/Csm/LegacyBiosDxe), otherwise Ahci devices
won't appear as Legacy entries.
On Thu, Aug 21, 2014 at 12:55 PM, wrote:
> From: Reza Jelveh
>
> The SataController is moved to PcAtChipsetPk
ny benefit to examine directly the D2H FIS Status
Register when D2H is received, instead of combining the two cases?
Thanks,
A. Sava
On Mon, Aug 25, 2014 at 3:44 AM, Tian, Feng wrote:
> My understanding is when D2H or PIO Setup FIS is received, the PxTFD
> gets updated with the content of
Regarding this, don't you think there's also need to check PxTFD for error
in the case D2H is received?
On Friday, August 22, 2014, Tian, Feng wrote:
> Good to me.
>
> Reviewed-by: Feng Tian >
>
> -Original Message-
> From: reza.jel...@tuhh.de [mailto:reza.jel...@tuhh.de
> ]
> Sent: Thu
vell would be one.
So, for both of them, it means that your patch will not break out at all,
as it will never get to check:
if (PrdCount == DataCount) { .. }
Cheers,
A. Sava
On Wed, Aug 13, 2014 at 4:04 AM, Tian, Feng wrote:
> Hi, Reza
>
> Thanks for your effort, Reza. I made a
Hi Reza,
Take note that regarding SataControllerDxe, there still remains a problem
that effects Qemu functionality.
On this query:
Data32 = AhciReadReg (PciIo, R_AHCI_CAP);
SataPrivateData->IdeInit.ChannelCount = (UINT8) ((Data32 & B_AHCI_CAP_NPS)
+ 1);
qemu seems to always report 1 channel. T
Hi Feng & Reza,
In Qemu's case, it won't break out on a Setup FIS, because currently for
PIO commands, Qemu does not put at all a PIO Setup FIS at the end, but only
a D2H FIS. Perhaps other controllers with a similar problem also have
similar implementations.
T
heck for EbdaAddress < 0x9A000 is just a
safety check, in case a given board did not properly contain EBDA address
at 0x40E. As far as I know EBDA should not go below 0x9A000 in any
implementation, but this specific range check may be reconsidered.
Thanks,
A. Sava
On Wed, Dec 25, 2013 at 10:12
Hello, are there any updates regarding this issue?
Thanks
A. Sava
On Wed, Dec 25, 2013 at 10:25 AM, Yao, Jiewen wrote:
> Good suggestion. I agree.
>
>
>
> Thank you
>
> Yao Jiewen
>
>
>
> *From:* A. Sava [mailto:asava@gmail.com]
> *Sent:* Wednesday, De
Hello,
DuetPkg/DxeIpl/HobGeneration.c @ PrepareHobMemory() allocates its memory
using fixed predefined addresses:
//
// Prepare Low Memory
// 0x18 pages is 72 KB.
//
gHob->MemoryFreeUnder1MB.ResourceLength = EFI_MEMORY_BELOW_1MB_END -
EFI_MEMORY_BELOW_1MB_START;
gHob->MemoryFreeU
There is a problem starting in edk2 r14587 - DXE phase may halt at
initialising PCD when PEI is empty.
The problem is at MdeModulePkg/Universal/PCD/Dxe/Service.c @
BuildPcdDxeDataBase ():
GuidHob = GetFirstGuidHob (&gPcdDataBaseHobGuid);
if (GuidHob != NULL) {
//
// If no PEIMs use d
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