I have an approach towards getting my Voltage ratings and required creepage/clearance that I would like feedback on.
See email inline To summarize the email attached: Application LV power systems mains monitoring in polyphase application. Terminal Rating 400VL:N/G and 600/690 L:L (UL/IEC), CAT III, PD 2, 3000m to IEC/UL 61010-1, requires ~ 6.3mm creepage/Clearance between phases. The pin to pin spacing edge to edge is just that but on pcb the solder pad cuts this down to 5.5mm with an oval pad. So how to get the 6.3mm? My approach Starting with a Phoenix Contact PC4 RA header https://www.phoenixcontact.com/online/portal/us?uri=pxc-oc-itemdetail:pid=1804797 <https://www.phoenixcontact.com/online/portal/us?uri=pxc-oc-itemdetail:pid=1804797&library=usen&tab=1> &library=usen&tab=1 Each terminal has two pcb plated through hole connections. I would like to cut off alternating pins from the header to form a Zig Zag pattern on the pcb. Note that my load is very small 5M ohms to ground so current rating should not be an issue application wise. The pins cut flush with header base. The pcb would have no pad for each cut off pin. This would give me the clearance and creepage I need due to the phase to phase voltage of 600V UL or 690 IEC. Issues * What would UL think of this? This is my biggest concern * Obviously affects current rating but my application is way below 1A. * Load will be a reinforced limiting impedance (resistor) * Could it just be a review issue in the submittal? * Is this a risky approach? Should I have a small project to review…. * Exposed Base metal on cut off pin – some corrosion possibly * I will coat area with humiseal, could have slots in pcb to allow coating to migrate to header side of pcb. * Mechanical strength reduced, * I will use side mounts that allow header to be screwed to the pcb. Thanks Chris Wells From: Chris Wells <radioactive55...@comcast.net> Sent: Saturday, October 26, 2019 3:36 PM To: 'EMC-PSTC@LISTSERV.IEEE.ORG' <EMC-PSTC@LISTSERV.IEEE.ORG> Subject: Terminal block pitch pcb creepage/clearance 400VL:N/G; 600/690 L:L CAT III, PD2, 3Km elevation I want to monitor mains of polyphase power systems VA/VB/VC/VN using EN/UL 61010-1 Ratings: 400VL:N/G; 600/690 L:L CAT III, PD2, 3Km elevation Issue I see is to get the phase to phase spacings on my terminal block. Requirements in Annex K are 5.5mm at 2Km but go up to ~ 6.3mm at 3Km. I would like to use a 4 position 7.62mm pitch terminal block and with oval pcb pads we can manage 5.5mm spacing between the plated through hole pcb pads. Hope to use a Phoenix Contact Combicon right angle header and matching terminal plug. Wire size max would be 14 AWG. I could slot the pcb between phases and coat the pcb in this area with Humiseal or similar. A competitor is claiming the same specs using same standard using coatings/slot but I do not see how they navigate the standard to claim their ratings t My take on the coating is that just reduces the effective pollution degree and the tables give no relief in that regard at PD1. Q - can the coating be considered more of a potting? Q - Are there any angles to pursue that would give use what we want? Or other ideas on how to terminate? An alternative is to use a 5.08mm pitch 7 position terminal block and depopulate the even positions. Most of the larger pitch terminal blocks are designed for high current and are too massive. Your thoughts/suggestions? Thanks Chris Wells - ---------------------------------------------------------------- This message is from the IEEE Product Safety Engineering Society emc-pstc discussion list. To post a message to the list, send your e-mail to <emc-p...@ieee.org> All emc-pstc postings are archived and searchable on the web at: http://www.ieee-pses.org/emc-pstc.html Attachments are not permitted but the IEEE PSES Online Communities site at http://product-compliance.oc.ieee.org/ can be used for graphics (in well-used formats), large files, etc. Website: http://www.ieee-pses.org/ Instructions: http://www.ieee-pses.org/list.html (including how to unsubscribe) List rules: http://www.ieee-pses.org/listrules.html For help, send mail to the list administrators: Scott Douglas <sdoug...@ieee.org> Mike Cantwell <mcantw...@ieee.org> For policy questions, send mail to: Jim Bacher: <j.bac...@ieee.org> David Heald: <dhe...@gmail.com>
