Hi! I have a fast ethernet design that does not pass
EMI from 30 to 100mhz and based on the scan it is
common mode noise. In my design i have the phy
connected to xfmr1--choke1---connector---I/O
card---xfmr2choke2---rj21---cables---patch
panel---rj45.
Now, if I use shielded cables from RJ21 to
ith unshielded cables, we have found that
> on multi-layer PCBs that has
> a good low impedence multi-point grounding system,
> the use on a continuous 0
> volt plane across the whole PCB works the best.
>
> Hope this helps
>
> Kind regards,
> Chris.
>
>
>
>
&
Hi! I had a question regarding meeting EMI on my board
for CISPR. I have a Fast Ethernet card and the 125MHz
Fast Ehternet fails the CISPR in the 30Mhz to 100Mhz
limit.
In the layout care has been taken to isolate the
chassis or quiet ground from Digital ground by
isolating the ground from the se
Hi! I had a question regarding the use of a resistor
between TIP/RING of E1 interface before the protection
circuitry.
1)on the E1 interface there is protection circuitry
but the designer wants to put befoer this circuitry
i.e. on line side a 120ohm resistor between TIP/RING.
The resistor mfgr. gu
Hi! I had recently posted a question to SI on the
testing requirements for T1/E1 i.e. EMC requirements
and I wanted to get some more feedback from this list
to make some decisions.
For our current T1/T3 products we don't for any
lightning tests since our product sits in the CO and
presumably we wi
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