Re: PCB layout question for good EMC performance

layout question for good EMC performance owner-emc-pstc@majordo mo.ieee.org

Re: PCB layout question for good EMC performance

Thanks to all who replied on this question. Ken Javor -- From: emccom...@aol.com To: dave.clem...@motorola.com, ken.ja...@emccompliance.com, emc-p...@majordomo.ieee.org Subject: Re: PCB layout question for good EMC performance Date: Fri, Jun 7, 2002, 6:00 PM Hi Ken, Rent's Rule

Re: PCB layout question for good EMC performance

Hi Ken, Rent's Rule (spelled as in Howard and Graham's book) with a worked example is on pages 216-217. Good Luck with your problem, Thurman J. (Bill) Ritenour EMC Compliance LLC 4575 Sioux Drive #303 Boulder, CO 80303 303-543-7404 emccom...@aol.com

RE: PCB layout question for good EMC performance

://www.motorola.com/globalcompliance/ -Original Message- From: Ken Javor [mailto:ken.ja...@emccompliance.com] Sent: Friday, June 07, 2002 4:20 PM To: emc-p...@majordomo.ieee.org Subject: PCB layout question for good EMC performance I have a problem where a very large number of chips are mounted

PCB layout question for good EMC performance

I have a problem where a very large number of chips are mounted on a very small board. The ground plane looks like Swiss cheese and there is ground bounce accordingly. For future reference, is there a rule-of-thumb for how much PCB area should be allocated per number of IC chips/pins so as to