take
several seconds for it to re-establish and some routing information may have
to be re-learned).
Gary
-Original Message-
From: Doug McKean [mailto:dmck...@corp.auspex.com]
Sent: Friday, July 27, 2001 8:03 AM
To: EMC-PSTC Discussion Group
Subject: Re: SONET ESD performance
I beg
I beg to disagree. I have reservations about no error criteria.
That's imposing a far greater restriction on equipment than
Criteria A for immunity. Now granted the immunity standards
are in a different spirit than the Bellcore Standards. But, it would
seem as though the errored second is more
Debatable in my experience which is not a lot.
There's two totally different standards for errors.
One's a bit error limit and the other is a time
errored limit.
An errored second can have any amount of
errors during that second. It's not a bit error limit.
It's a time errored limit.
opinions only]
-Original Message-
From: Martin Garwood [mailto:mgarw...@approvalspecialists.com]
Sent: Wednesday, July 25, 2001 8:01 PM
To: Scott Lemon; emc-p...@majordomo.ieee.org
Subject:Re: SONET ESD performance
Scott,
The permissible errors relate back to your
Scott,
The permissible errors relate back to your system specification (IRS) as it
relates to BERs. For an OC-48 interface you may be working off a rate of
around
10^-12 and it only takes a few weeks to test that !!, so the easiest and
short answer is, no bit errors should be observed during
Hi Scott and the group,
Just a thought... If the equipment you are testing responds unfavorably
to something the environment, it does not matter that you pass GR-1089.
And, I have seen lots of stuff that affected lightwave equipment not
covered under 1089 that got the operating companies pretty
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