Re: [etherlab-users] SKIPPED datagram using Igh EtherCAT master porting for Linux OS on CyconeV SoC

2015-02-19 Thread Mike O'Connor
On 17/02/2015 11:38 am, Gavin Lambert wrote: On standard x86 hardware, you’re unlikely to get much better than 4 ms cycle rates even on Linux+PREEMPT_RT if you’re using the generic driver. Since you’re using more cut-down hardware, it wouldn’t surprise me if this were more limited. On our

[etherlab-users] SKIPPED datagram using Igh EtherCAT master porting for Linux OS on CyconeV SoC

2015-02-16 Thread Brian Cheng
Hi, Does anyone could run short cycle(1ms) well using Igh EtherCAT master for linux-RT of Cyclone V (ARM CortexA9 925Mhz) ? I got the linux-socfpga.git for downloading Linux-3.10-ltsi-rt. I already put the EtherCAT module application on the Linux-RT Helio board for Cyclone V. It could run well

Re: [etherlab-users] SKIPPED datagram using Igh EtherCAT master porting for Linux OS on CyconeV SoC

2015-02-16 Thread Gavin Lambert
cut-down hardware, it wouldn’t surprise me if this were more limited. From: etherlab-users [mailto:etherlab-users-boun...@etherlab.org] On Behalf Of Brian Cheng Sent: Tuesday, 17 February 2015 13:44 To: etherlab-users@etherlab.org Subject: [etherlab-users] SKIPPED datagram using Igh EtherCAT