On Thu, 2010-09-16 at 05:27 +0200, Mattias Mattsson wrote:
> On Thu, Sep 16, 2010 at 00:23, Andrew Cleveland
> wrote:
> > Hello,
> >
> > I have an ECS Geforce6100SM-M (v1.0 I believe); here is the output of
> > 'flashrom -V', 'lspci -nnvvvxxx', and 'superiotool -deV' as requested on
> > IRC.
> >
On Thu, 2010-09-16 at 05:27 +0200, Mattias Mattsson wrote:
> On Thu, Sep 16, 2010 at 00:23, Andrew Cleveland
> wrote:
> > Hello,
> >
> > I have an ECS Geforce6100SM-M (v1.0 I believe); here is the output of
> > 'flashrom -V', 'lspci -nnvvvxxx', and 'superiotool -deV' as requested on
> > IRC.
> >
On Thu, Sep 16, 2010 at 00:23, Andrew Cleveland wrote:
> Hello,
>
> I have an ECS Geforce6100SM-M (v1.0 I believe); here is the output of
> 'flashrom -V', 'lspci -nnvvvxxx', and 'superiotool -deV' as requested on
> IRC.
>
> Official BIOS download:
> http://download.ecsusa.com/dlfileecs/bios/mb/p4/
On Wed, Sep 15, 2010 at 16:34, Joshua Roys wrote:
> Hello,
>
> Awesome! I'm glad you got it working.
>
> On 09/15/2010 06:19 AM, Carl-Daniel Hailfinger wrote:
>> Funny. The 0xc6f access looks very similar to parts of the SB400 chipset
>> enable. (Side note: we should ask AMD if the SB400 chipset
Author: mhm
Date: Thu Sep 16 02:51:51 2010
New Revision: 1176
URL: http://flashrom.org/trac/flashrom/changeset/1176
Log:
Add chip definitions for the folowing chips:
Bright BM29F040
Hyundai HY29F040A
Macronix MX29F040
Also add chip IDs for
Bright BM29F400T/B
Datasheets:
http://www.ezoflash.com/
On Wed, Sep 15, 2010 at 17:49, Carl-Daniel Hailfinger
wrote:
> On 15.09.2010 04:04, Mattias Mattsson wrote:
>> This patch changes the prefix of chip constant #defines in the following way:
>>
>> AM_nnn -> AMD_AMnnn
>> AT_nnn -> ATMEL_ATnnn
>> EN_nnn -> EON_ENnnn
>> MBMn
Am Mittwoch, den 15.09.2010, 20:14 +0200 schrieb STEMMELIN, FREDERIC
(FREDERIC)** CTR **:
> NOT WORKING is writing from original Tyan BIOS image (Error: Image
> size doesn't match, 2895V106.wph,
> ftp://ftp.tyan.com/bios/S2895_v106.zip)
This is normal for phoenix images (flashed by winphlash or phl
On Wed, 15 Sep 2010, Carl-Daniel Hailfinger wrote:
> On 04.02.2010 07:13, Sean Nelson wrote:
> > I'd like Uwe, Stepan, or Carl-Daniel to test this and send an ack/nack.
> >
> > On 1/31/10 8:07 AM, Anders Juel Jensen wrote:
> >> On Sunday 31 January 2010 06:33:12 Sean Nelson wrote:
> >>> Add a rese
On 15.09.2010 04:04, Mattias Mattsson wrote:
> This patch changes the prefix of chip constant #defines in the following way:
>
> AM_nnn -> AMD_AMnnn
> AT_nnn -> ATMEL_ATnnn
> EN_nnn -> EON_ENnnn
> MBMnnn -> FUJITSU_MBMnnn
> MX_ID -> MACRONIX_ID
> MX_nnn -> MACRON
Author: hailfinger
Date: Wed Sep 15 16:47:56 2010
New Revision: 1174
URL: http://flashrom.org/trac/flashrom/changeset/1174
Log:
Add chipset enable for Broadcom OSB4.
No docs available.
Signed-off-by: Joshua Roys
Acked-by: Carl-Daniel Hailfinger
Modified:
trunk/chipset_enable.c
Modified: t
Hello,
Awesome! I'm glad you got it working.
On 09/15/2010 06:19 AM, Carl-Daniel Hailfinger wrote:
> Funny. The 0xc6f access looks very similar to parts of the SB400 chipset
> enable. (Side note: we should ask AMD if the SB400 chipset enable is
> correct.)
>
Yes, I noticed the same thing- henc
On 15.09.2010 12:27, Matthias Kretz wrote:
> Hi,
>
> On Wednesday 15 September 2010 12:02:50 Carl-Daniel Hailfinger wrote:
>
>> Patch at http://patchwork.coreboot.org/patch/1946/
>>
>> Could you please reply with a full log from "flashrom -V -r foo.rom" and
>> if the log says "Disabling write.",
Author: hailfinger
Date: Wed Sep 15 14:02:07 2010
New Revision: 1173
URL: http://flashrom.org/trac/flashrom/changeset/1173
Log:
AMD SB700 and later have an integrated microcontroller (IMC) which runs
from shared flash. The IMC will happily issue reads while we write,
issue writes while we read, an
On Wed, Sep 15, 2010 at 12:02:50PM +0200, Carl-Daniel Hailfinger wrote:
> > Signed-off-by: Carl-Daniel Hailfinger
Was now tested on hardware.
Acked-by: Uwe Hermann
Uwe.
--
http://hermann-uwe.de | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org
___
On 04.02.2010 07:13, Sean Nelson wrote:
> I'd like Uwe, Stepan, or Carl-Daniel to test this and send an ack/nack.
>
> On 1/31/10 8:07 AM, Anders Juel Jensen wrote:
>> On Sunday 31 January 2010 06:33:12 Sean Nelson wrote:
>>> Add a reset to probe_jedec before we read the Chip's IDs.
>>> Signed-off-b
Am Mittwoch, den 15.09.2010, 13:01 +0200 schrieb Carl-Daniel Hailfinger:
> >> Peter, could you please attach /proc/ioports and check if dmesg mentions
> >> 0xc06 or 0xc6f or anything close to that?
> >>
> >
> > Attached /proc/ioports and dmesg contents.
> >
> > /proc/ioports:
> > [...]
> > 0c1
On 15.09.2010 12:31, Peter Lemenkov wrote:
> Hello!
>
> 2010/9/15 Carl-Daniel Hailfinger :
>
>
>>> --- a/chipset_enable.c
>>> +++ b/chipset_enable.c
>>> @@ -802,6 +802,23 @@ static int enable_flash_ck804(struct pci_dev *dev,
>>> const char *name)
>>> return 0;
>>> }
>>>
>>> +static int e
Hello!
2010/9/15 Carl-Daniel Hailfinger :
>> --- a/chipset_enable.c
>> +++ b/chipset_enable.c
>> @@ -802,6 +802,23 @@ static int enable_flash_ck804(struct pci_dev *dev,
>> const char *name)
>> return 0;
>> }
>>
>> +static int enable_flash_osb4(struct pci_dev *dev, const char *name)
>> +{
Hi,
On Wednesday 15 September 2010 12:02:50 Carl-Daniel Hailfinger wrote:
> Patch at http://patchwork.coreboot.org/patch/1946/
>
> Could you please reply with a full log from "flashrom -V -r foo.rom" and
> if the log says "Disabling write.", please also reply with either
Log attached.
Tested-by
On 15.09.2010 12:20, Carl-Daniel Hailfinger wrote:
> On 15.09.2010 12:13, Michael Karcher wrote:
>
>> Am Mittwoch, den 15.09.2010, 11:58 +0200 schrieb Carl-Daniel Hailfinger:
>>
>>
>>> Delay between probe and subsequent operations.
>>>
>>>
>> [...]
>>
>>
>>> Signed-of
On 15.09.2010 12:13, Michael Karcher wrote:
> Am Mittwoch, den 15.09.2010, 11:58 +0200 schrieb Carl-Daniel Hailfinger:
>
>> Delay between probe and subsequent operations.
>>
> [...]
>
>> Signed-off-by: Carl-Daniel Hailfinger
>>
> Acked-by: Michael Karcher
>
Thanks for the quic
Author: hailfinger
Date: Wed Sep 15 12:20:16 2010
New Revision: 1172
URL: http://flashrom.org/trac/flashrom/changeset/1172
Log:
Delay between probe and subsequent operations.
Some flash chips need time to exit ID mode, and while we take care of
correct timing for the matching probe, subsequent pr
On 15.09.2010 11:10, Joshua Roys wrote:
> Attached is a patch that might get your flash chip to appear- a
> chipset enable was put into place, and some flash chips were added
> that could have been used in your board. It's possible but unlikely
> that write would work, mostly due to the following:
Am Mittwoch, den 15.09.2010, 11:58 +0200 schrieb Carl-Daniel Hailfinger:
> Delay between probe and subsequent operations.
[...]
> Signed-off-by: Carl-Daniel Hailfinger
Acked-by: Michael Karcher
Regards,
Michael Karcher
___
flashrom mailing list
fla
Hi Matthias,
I'm sorry, I forgot to CC you.
On 15.09.2010 11:38, Carl-Daniel Hailfinger wrote:
> New version, fixes a variable misuse found by Uwe. Thanks for the review.
>
> AMD SB700 and later have an integrated microcontroller (IMC) which runs
> from shared flash. The IMC will happily issue re
Delay between probe and subsequent operations.
Some flash chips need time to exit ID mode, and while we take care of
correct timing for the matching probe, subsequent probes may have
totally different timing, and that can lead to garbage responses from
the flash chip during the first accesses afte
Hello,
Attached is a patch that might get your flash chip to appear- a
chipset enable was put into place, and some flash chips were added
that could have been used in your board. It's possible but unlikely
that write would work, mostly due to the following:
On Tue, Sep 14, 2010 at 7:33 AM, Carl-
New version, fixes a variable misuse found by Uwe. Thanks for the review.
AMD SB700 and later have an integrated microcontroller (IMC) which runs
from shared flash. The IMC will happily issue reads while we write,
issue writes while we read, and generally cause lots of havoc due to the
concurrent
2010/9/15 Peter Lemenkov :
> Great work - now I can see the flashchip. Also, please, sed -i
> s,read_memapped,read_memmapped,g in your patch. See flashrom's log
> attached.
This was only probing and here is a log of successful read attempt (attached).
> Tested-by: Peter Lemenkov
Likewise.
--
Hello Joshua.
2010/9/15 Joshua Roys :
> Hello,
>
> Attached is a patch that might get your flash chip to appear- a
> chipset enable was put into place, and some flash chips were added
> that could have been used in your board.
Great work - now I can see the flashchip. Also, please, sed -i
s,read_
following is from a Zotac ionitx-a-u . I can provide any other info
needed. I'm pretty handy on the ol console, and I like to support
open source.
flashrom v0.9.1-r946
No coreboot table found.
DMI string system-manufacturer: "To Be Filled By O.E.M."
DMI string system-product-name: "To Be Filled
-- Forwarded message --
From: Shahar Or
Date: Wed, 15 Sep 2010 08:59:02 +0200
Subject: Re: flashrom test on MSI PM8M3-V 4.1
To: Uwe Hermann
Dear ones,
It is the V H, actually. Thanks for noticing.
Blessings,
Shahar
On 9/15/10, Uwe Hermann wrote:
> On Sat, Sep 04, 2010 at 11:3
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