The PIC32MX chips have one or two shadow sets, on the systems with only
one shadow set it is hardcoded to the highest priority interrupt (7)
I have implemented detection of shadow register use, in this case the
registers do not get pushed on stack, that saves quite a few cpu-cycles
in that cas
Am 13.08.2016 um 18:57 schrieb Michael Ring:
> Hi!
>
> I am trying to bring interrupt handling routine size down (and speed up) for
> mipsel-embedded target.
>
> I need to use inline assembler routines like this one
>
> procedure TSystemCore.setCoreTimerComp(value : longWord); assembler;
> nos
