From: J. Gareth Moreton
To:
> Are you able to dump the nodes as well with -an? (You'll need to define
> -dEXTDEBUG though) That might give some clues behind the presence of
> that movslq instruction.
building compiler with -dEXTDEBUG does not work for me
make singlezipinstall OS_TARGET=linu
Are you able to dump the nodes as well with -an? (You'll need to define
-dEXTDEBUG though) That might give some clues behind the presence of
that movslq instruction.
Gareth aka. Kit
On 04/02/2020 21:15, Marģers . via fpc-devel wrote:
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Subject: Re: [fpc-devel] g
test plz ignore
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Subject: Re: [fpc-devel] generate assembler with no clear purpose MOV
Date: otrd., 4 febr. 2020, 22:24
From: J. Gareth Moreton
To:
> To hazard a guess, it's sign-extending to the CPU word size as an
> intermediate step. It's not something the peephole optimizer
To hazard a guess, it's sign-extending to the CPU word size as an
intermediate step. It's not something the peephole optimizer can easily
eliminate. Do the register allocations give any clues before that
instruction?
Gareth aka. Kit
On 04/02/2020 18:50, Marģers . via fpc-devel wrote:
p.s
p.s. tested execution speed and there is no measurable difference.
> asm code
> # [109] bit:= longint(1) shl k;
> movslq %ecx,%rdx
> # Register r8d allocated
> movl $1,%r8d
> # Register edx,edx allocated
> shlx %edx,%r8d,%edx
> # Register r8d released
> # Reg
hi
example code:
function roo(lk:longint):byte;
var k : longint;
bit : longint;
num : byte;
begin
num:=0;
for k:=0 to 25 do
begin
bit:= longint(1) shl k;
if (lk and bit) <> 0 then
begin
lk:=lk xor bit;
inc(num);
Hi everyone,
I have an idea in regards to improving compilation speed. It mostly applies to
the x86 family, but I see no
reason why it cannot be platform-agnostic. The idea is basically this:
- The optimisation level selected (-O1, -O2, -O3/-O4) dictates the MAXIMUM
number of times Pass 1 is
