Re: [fpc-devel] Code generator issue for Cortex-M0 chips in trunk

The patch worked, generated assembler looks ok, will test on device this evening Am 08.08.14 um 14:27 schrieb Nico Erfurth: On 08.08.14 10:28, Michael Ring wrote: There seems to be a bug in the codegenerator for armv6m thumb code. tst r0,#-2147483648 is not valid armv6m assembler code, docum

Re: [fpc-devel] Code generator issue for Cortex-M0 chips in trunk

On 08.08.14 10:28, Michael Ring wrote: > There seems to be a bug in the codegenerator for armv6m thumb code. > > tst r0,#-2147483648 > > is not valid armv6m assembler code, documentation says that tst only can > use registers: > > TST Rn, Rm Please try the attached patch, it should solve the pr

Re: [fpc-devel] Code generator issue for Cortex-M0 chips in trunk

Will do so Michael Am 08.08.14 um 13:57 schrieb Sven Barth: Am 08.08.2014 10:29 schrieb "Michael Ring" >: > > There seems to be a bug in the codegenerator for armv6m thumb code. > > tst r0,#-2147483648 > > is not valid armv6m assembler code, documentation sa

Re: [fpc-devel] Code generator issue for Cortex-M0 chips in trunk

Am 08.08.2014 10:29 schrieb "Michael Ring" : > > There seems to be a bug in the codegenerator for armv6m thumb code. > > tst r0,#-2147483648 > > is not valid armv6m assembler code, documentation says that tst only can use registers: > > TST Rn, Rm > > where: > Rn Is the register holding the first o

[fpc-devel] Code generator issue for Cortex-M0 chips in trunk

There seems to be a bug in the codegenerator for armv6m thumb code. tst r0,#-2147483648 is not valid armv6m assembler code, documentation says that tst only can use registers: TST Rn, Rm where: Rn Is the register holding the first operand. Rm The register to test against. Cortex-M0+ Devic