Re: Intel CPU design flaw - FreeBSD affected? // disabling _R_DTSC

2018-01-05 Thread Andrew Reilly
On Fri, Jan 05, 2018 at 02:27:40AM +0800, blubee blubeeme wrote: > I'd love to see if RISC-V is vulnerable to this? > > I think they are in the best position to capitalize on this clusterfk... It's a micro-architecture flaw, not an instruction set flaw, so just as for ARM and amd64, it will depen

Re: Intel CPU design flaw - FreeBSD affected?

2018-01-05 Thread Erich Dollansky
Hi, On Thu, 4 Jan 2018 15:33:46 +0100 Stefan Esser wrote: > Am 04.01.18 um 12:56 schrieb Darren Reed: > > On 4/01/2018 11:51 AM, Mark Heily wrote: > >> On Jan 2, 2018 19:05, "Warner Losh" wrote: > >> > >> The register article says the specifics are under embargo still. > >> That would make it

Re: Programmatically cache line

2018-01-05 Thread David Chisnall
On 5 Jan 2018, at 02:46, Jon Brawn wrote: > This idea of Arm big.LITTLE systems having cache lines of different lengths > really, really bothers me - how on earth is the cache coherency supposed to > work in such a system? I doubt the usual cache coherency protocols would work > - probably need