On 11-Nov-2003 John Hay wrote:
>> >> >> With the new interrupt code I get:
>> >> >> <...>
>> >> >> OK boot
>> >> >> cpuid = 0; apic id = 00
>> >> >> instruction pointer = 0x0:0xa00
>> >> >> stack pointer = 0x0:0xffe
>> >> >> frame pointer = 0x0:0x0
>> >> >> code segment
> >> >> With the new interrupt code I get:
> >> >> <...>
> >> >> OK boot
> >> >> cpuid = 0; apic id = 00
> >> >> instruction pointer = 0x0:0xa00
> >> >> stack pointer = 0x0:0xffe
> >> >> frame pointer = 0x0:0x0
> >> >> code segment= base 0x0, limit 0x0, type 0x0
On 10-Nov-2003 John Hay wrote:
> On Mon, Nov 10, 2003 at 02:12:56PM -0500, John Baldwin wrote:
>>
>> On 10-Nov-2003 John Hay wrote:
>> >>
>> >> With the new interrupt code I get:
>> >> <...>
>> >> OK boot
>> >> cpuid = 0; apic id = 00
>> >> instruction pointer = 0x0:0xa00
>> >> stack pointer
On Mon, Nov 10, 2003 at 02:12:56PM -0500, John Baldwin wrote:
>
> On 10-Nov-2003 John Hay wrote:
> >>
> >> With the new interrupt code I get:
> >> <...>
> >> OK boot
> >> cpuid = 0; apic id = 00
> >> instruction pointer = 0x0:0xa00
> >> stack pointer = 0x0:0xffe
> >> frame pointer
On Mon, Nov 10, 2003 at 02:12:56PM -0500, John Baldwin wrote:
>
> On 10-Nov-2003 John Hay wrote:
> >>
> >> With the new interrupt code I get:
> >> <...>
> >> OK boot
> >> cpuid = 0; apic id = 00
> >> instruction pointer = 0x0:0xa00
> >> stack pointer = 0x0:0xffe
> >> frame pointer
On 10-Nov-2003 John Hay wrote:
>>
>> With the new interrupt code I get:
>> <...>
>> OK boot
>> cpuid = 0; apic id = 00
>> instruction pointer = 0x0:0xa00
>> stack pointer = 0x0:0xffe
>> frame pointer = 0x0:0x0
>> code segment= base 0x0, limit 0x0, type 0x0
>>
On 10-Nov-2003 Marius Strobl wrote:
> On Thu, Nov 06, 2003 at 12:22:45PM -0500, John Baldwin wrote:
>>
>> On 06-Nov-2003 Harti Brandt wrote:
>> > JB>I figured out what is happenning I think. You are getting a spurious
>> > JB>interrupt from the 8259A PIC (which comes in on IRQ 7). The IRR regis
>
> With the new interrupt code I get:
> <...>
> OK boot
> cpuid = 0; apic id = 00
> instruction pointer = 0x0:0xa00
> stack pointer = 0x0:0xffe
> frame pointer = 0x0:0x0
> code segment= base 0x0, limit 0x0, type 0x0
> = DPL 0, pres 0, de
On Thu, Nov 06, 2003 at 12:22:45PM -0500, John Baldwin wrote:
>
> On 06-Nov-2003 Harti Brandt wrote:
> > JB>I figured out what is happenning I think. You are getting a spurious
> > JB>interrupt from the 8259A PIC (which comes in on IRQ 7). The IRR register
> > JB>lists pending interrupts still w
On Fri, 7 Nov 2003, Stefan [iso-8859-1] Eßer wrote:
> On 2003-11-07 20:04 +1100, Bruce Evans <[EMAIL PROTECTED]> wrote:
> > However, using the apic almost doubles the overheads for the a45 cases.
> > This seems to be due to extra interrupts. The UART and/or driver already
>
> Just another data po
On Thu, 6 Nov 2003, John Baldwin wrote:
JB>
JB>On 06-Nov-2003 Harti Brandt wrote:
JB>> JB>I figured out what is happenning I think. You are getting a spurious
JB>> JB>interrupt from the 8259A PIC (which comes in on IRQ 7). The IRR register
JB>> JB>lists pending interrupts still waiting to be ser
On Thu, 6 Nov 2003, John Baldwin wrote:
> On 06-Nov-2003 Harti Brandt wrote:
> > JB>I figured out what is happenning I think. You are getting a spurious
> > JB>interrupt from the 8259A PIC (which comes in on IRQ 7). The IRR register
> > JB>lists pending interrupts still waiting to be serviced.
On 06-Nov-2003 Harti Brandt wrote:
> JB>I figured out what is happenning I think. You are getting a spurious
> JB>interrupt from the 8259A PIC (which comes in on IRQ 7). The IRR register
> JB>lists pending interrupts still waiting to be serviced. Try using
> JB>'options NO_MIXED_MODE' to stop u
On Wed, 5 Nov 2003, John Baldwin wrote:
JB>
JB>On 05-Nov-2003 Harti Brandt wrote:
JB>> On Tue, 4 Nov 2003, John Baldwin wrote:
JB>>
JB>> JB>
JB>> JB>On 04-Nov-2003 Harti Brandt wrote:
JB>> JB>> On Tue, 4 Nov 2003, Harti Brandt wrote:
JB>> JB>>
JB>> JB>> HB>On Tue, 4 Nov 2003, John Baldwin wrote:
J
On 05-Nov-2003 Harti Brandt wrote:
> On Tue, 4 Nov 2003, John Baldwin wrote:
>
> JB>
> JB>On 04-Nov-2003 Harti Brandt wrote:
> JB>> On Tue, 4 Nov 2003, Harti Brandt wrote:
> JB>>
> JB>> HB>On Tue, 4 Nov 2003, John Baldwin wrote:
> JB>> HB>
> JB>> HB>JB>
> JB>> HB>JB>On 04-Nov-2003 Harti Brandt wr
Another data point: I can't get my Asus A7M266-D to boot with the
new interrupt code at all, perhaps because I have an Adaptec 39160.
Whether acpi is on or off, whether it's in the kernel config or not,
booting always hangs right after "waiting 10 sec for scsi to settle"
and "0 scb's aborted". I'
On Wed, 5 Nov 2003, Harti Brandt wrote:
HB>On Tue, 4 Nov 2003, John Baldwin wrote:
HB>
HB>JB>
HB>JB>On 04-Nov-2003 Harti Brandt wrote:
HB>JB>> On Tue, 4 Nov 2003, Harti Brandt wrote:
HB>JB>>
HB>JB>> HB>On Tue, 4 Nov 2003, John Baldwin wrote:
HB>JB>> HB>
HB>JB>> HB>JB>
HB>JB>> HB>JB>On 04-Nov-2003
On 04-Nov-2003 Harti Brandt wrote:
> On Tue, 4 Nov 2003, Harti Brandt wrote:
>
> HB>On Tue, 4 Nov 2003, John Baldwin wrote:
> HB>
> HB>JB>
> HB>JB>On 04-Nov-2003 Harti Brandt wrote:
> HB>JB>>
> HB>JB>> Hi,
> HB>JB>>
> HB>JB>> I have an ASUS system with 2 CPUs that I need to run at HZ=1. This
Hi.
> > I also have an ASUS motherboard with an Intel 875P
> > chipset.
>
> Can you post a dmesg? Note that if you want
> hyperthreading,
> you need to enable it in your BIOS. The ACPI (and
> soon the
> MPTable) drivers will not use HT CPUs unless HT is
> enabled in
> the BIOS. My test machine
On 04-Nov-2003 Harti Brandt wrote:
> On Tue, 4 Nov 2003, Harti Brandt wrote:
>
> HB>On Tue, 4 Nov 2003, John Baldwin wrote:
> HB>
> HB>JB>
> HB>JB>On 04-Nov-2003 Harti Brandt wrote:
> HB>JB>>
> HB>JB>> Hi,
> HB>JB>>
> HB>JB>> I have an ASUS system with 2 CPUs that I need to run at HZ=1. This
On Tue, 4 Nov 2003, Harti Brandt wrote:
HB>On Tue, 4 Nov 2003, John Baldwin wrote:
HB>
HB>JB>
HB>JB>On 04-Nov-2003 Harti Brandt wrote:
HB>JB>>
HB>JB>> Hi,
HB>JB>>
HB>JB>> I have an ASUS system with 2 CPUs that I need to run at HZ=1. This
HB>JB>> worked until yesterday, but with the new interru
On Tue, 4 Nov 2003, Harti Brandt wrote:
HB>On Tue, 4 Nov 2003, John Baldwin wrote:
HB>
HB>JB>
HB>JB>On 04-Nov-2003 Harti Brandt wrote:
HB>JB>>
HB>JB>> Hi,
HB>JB>>
HB>JB>> I have an ASUS system with 2 CPUs that I need to run at HZ=1. This
HB>JB>> worked until yesterday, but with the new interru
On Tue, 4 Nov 2003, John Baldwin wrote:
JB>
JB>On 04-Nov-2003 Harti Brandt wrote:
JB>>
JB>> Hi,
JB>>
JB>> I have an ASUS system with 2 CPUs that I need to run at HZ=1. This
JB>> worked until yesterday, but with the new interrupt code it doesn't boot
JB>> anymore. It works for the standard HZ,
On 04-Nov-2003 Harti Brandt wrote:
>
> Hi,
>
> I have an ASUS system with 2 CPUs that I need to run at HZ=1. This
> worked until yesterday, but with the new interrupt code it doesn't boot
> anymore. It works for the standard HZ, but if I set HZ=1000 I get a double
> fault. I suspect a race c
On 04-Nov-2003 Claus Guttesen wrote:
> Hi.
>
>> I have an ASUS system with 2 CPUs that I need to run
>> at HZ=1. This
>> worked until yesterday, but with the new interrupt
>> code it doesn't boot
>> anymore. It works for the standard HZ, but if I set
>> HZ=1000 I get a double
>
> Compiled a
Hi.
> I have an ASUS system with 2 CPUs that I need to run
> at HZ=1. This
> worked until yesterday, but with the new interrupt
> code it doesn't boot
> anymore. It works for the standard HZ, but if I set
> HZ=1000 I get a double
Compiled a new kernel with source from Nov. 3'rd where
SMP and
Hi,
I have an ASUS system with 2 CPUs that I need to run at HZ=1. This
worked until yesterday, but with the new interrupt code it doesn't boot
anymore. It works for the standard HZ, but if I set HZ=1000 I get a double
fault. I suspect a race condition in the interrupt handling. My config
file
27 matches
Mail list logo
