Marco van de Voort wrote:
On Sat, Dec 08, 2007 at 03:43:30AM +0100, Ivan Voras wrote:
Which of the architectures FreeBSD supports (if any) have strict memory
alignment requirements? (in the sense that accessing a 32-bit integer
not aligned on a 32-bit address results in a hardware trap/excep
On Sat, Dec 08, 2007 at 03:43:30AM +0100, Ivan Voras wrote:
> Which of the architectures FreeBSD supports (if any) have strict memory
> alignment requirements? (in the sense that accessing a 32-bit integer
> not aligned on a 32-bit address results in a hardware trap/exception).
I do know that old
On Mon, Dec 31, 2007 at 08:30:35PM +0800, Erich Dollansky wrote:
> Hi,
>
> Kostik Belousov wrote:
>> On Mon, Dec 31, 2007 at 05:38:43PM +0800, Erich Dollansky wrote:
>>> Kostik Belousov wrote:
On Sat, Dec 29, 2007 at 01:12:04PM +0200, Kostik Belousov wrote:
> On Sat, Dec 29, 2007 at 12:14
Hi,
Kostik Belousov wrote:
On Mon, Dec 31, 2007 at 05:38:43PM +0800, Erich Dollansky wrote:
Kostik Belousov wrote:
On Sat, Dec 29, 2007 at 01:12:04PM +0200, Kostik Belousov wrote:
On Sat, Dec 29, 2007 at 12:14:11AM -0800, Kip Macy wrote:
I.e., it seems that gcc does not feel too guilty gener
On Mon, Dec 31, 2007 at 05:38:43PM +0800, Erich Dollansky wrote:
> Hi,
>
> Kostik Belousov wrote:
> >On Sat, Dec 29, 2007 at 01:12:04PM +0200, Kostik Belousov wrote:
> >>On Sat, Dec 29, 2007 at 12:14:11AM -0800, Kip Macy wrote:
> >
> >I.e., it seems that gcc does not feel too guilty generating una
Hi,
Kostik Belousov wrote:
On Sat, Dec 29, 2007 at 01:12:04PM +0200, Kostik Belousov wrote:
On Sat, Dec 29, 2007 at 12:14:11AM -0800, Kip Macy wrote:
I.e., it seems that gcc does not feel too guilty generating unaligned
half-word writes on i386. :(
this should not be a problem inside a cach
On Sun, Dec 30, 2007 at 11:18:08PM -0500, Mike Meyer wrote:
> On Sun, 30 Dec 2007 20:37:18 +0100 Bernd Walter <[EMAIL PROTECTED]> wrote:
> > On Sun, Dec 30, 2007 at 01:55:06PM -0500, Mike Meyer wrote:
> > > Ok, I'm a bit confused. Since you're talking about moving code from
> > > the x86 to the alp
On Sun, 30 Dec 2007 20:37:18 +0100 Bernd Walter <[EMAIL PROTECTED]> wrote:
> On Sun, Dec 30, 2007 at 01:55:06PM -0500, Mike Meyer wrote:
> > On Sun, 30 Dec 2007 10:34:33 +0100 Bernd Walter <[EMAIL PROTECTED]> wrote:
> > > On Sat, Dec 29, 2007 at 11:37:27PM +0100, Dag-Erling Smørgrav wrote:
> > > >
On Sun, Dec 30, 2007 at 01:55:06PM -0500, Mike Meyer wrote:
> On Sun, 30 Dec 2007 10:34:33 +0100 Bernd Walter <[EMAIL PROTECTED]> wrote:
> > On Sat, Dec 29, 2007 at 11:37:27PM +0100, Dag-Erling Smørgrav wrote:
> > > Wilko Bulte <[EMAIL PROTECTED]> writes:
> > > > In the past the alpha port had it t
On Sun, 30 Dec 2007 10:34:33 +0100 Bernd Walter <[EMAIL PROTECTED]> wrote:
> On Sat, Dec 29, 2007 at 11:37:27PM +0100, Dag-Erling Smørgrav wrote:
> > Wilko Bulte <[EMAIL PROTECTED]> writes:
> > > In the past the alpha port had it too.
> >
> > No, it was optional and defaulted to off.
>
> It was n
On Sat, Dec 29, 2007 at 01:12:04PM +0200, Kostik Belousov wrote:
> On Sat, Dec 29, 2007 at 12:14:11AM -0800, Kip Macy wrote:
> > Isn't it everything except x86?
> >
> > -Kip
> x86 has the AC bit in the eflags. The AM bit in cr0 is enabled by the
> kernel, and AC could be switched on by LD_PRELOADe
On Sat, Dec 29, 2007 at 11:37:27PM +0100, Dag-Erling Smørgrav wrote:
> Wilko Bulte <[EMAIL PROTECTED]> writes:
> > In the past the alpha port had it too.
>
> No, it was optional and defaulted to off.
It was never optional, since no alpha CPU can do missaligned access
Alphas can fix missaligned ac
On Sat, Dec 29, 2007 at 02:06:27PM -0800, Bakul Shah wrote:
>> (though the AMD29K could apparently generate
>> dummy bus cycles to limit the number of bit transitions on any cycle
>> to reduce the I/O load).
>
>Are you sure it was the amd29k? I don't recall anything like
>that
Ivan Voras <[EMAIL PROTECTED]> wrote:
> [EMAIL PROTECTED] wrote:
>
> > The degree to which a PowerPC imposes a strict alignment
> > requirement depends on both the particular processor model
> > and the operation being performed.
> >
> > For ordinary integer arithmetic and logical operations, new
[EMAIL PROTECTED] wrote:
> The degree to which a PowerPC imposes a strict alignment requirement
> depends on both the particular processor model and the operation
> being performed.
>
> For ordinary integer arithmetic and logical operations, newer
> PPC processors tend to be more tolerant (althou
"M. Warner Losh" <[EMAIL PROTECTED]> wrote:
> In message: <[EMAIL PROTECTED]>
> Ivan Voras <[EMAIL PROTECTED]> writes:
> : Which of the architectures FreeBSD supports (if any) have strict
> : memory alignment requirements? (in the sense that accessing a
> : 32-bit integer not aligned o
Wilko Bulte <[EMAIL PROTECTED]> writes:
> In the past the alpha port had it too.
No, it was optional and defaulted to off.
DES
--
Dag-Erling Smørgrav - [EMAIL PROTECTED]
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> (though the AMD29K could apparently generate
> dummy bus cycles to limit the number of bit transitions on any cycle
> to reduce the I/O load).
Are you sure it was the amd29k? I don't recall anything like
that (and am too lazy to dig out its datasheets!).
It too requiredd st
On Sat, Dec 29, 2007 at 06:03:15PM +0800, Erich Dollansky wrote:
>All RISC based designs need the alignment so that the CPU can fetch a CPU
>word in one go. CISC based designs do not have this limitiation.
It's more that the additional logic required to split a single memory
operation (load/store
Quoting M. Warner Losh, who wrote on Sat, Dec 29, 2007 at 12:22:21PM -0700 ..
> In message: <[EMAIL PROTECTED]>
> Ivan Voras <[EMAIL PROTECTED]> writes:
> : Which of the architectures FreeBSD supports (if any) have strict memory
> : alignment requirements? (in the sense that accessing a
In message: <[EMAIL PROTECTED]>
Ivan Voras <[EMAIL PROTECTED]> writes:
: Which of the architectures FreeBSD supports (if any) have strict memory
: alignment requirements? (in the sense that accessing a 32-bit integer
: not aligned on a 32-bit address results in a hardware trap/exception
Am 29.12.2007 um 13:01 schrieb Joerg Sonnenberger:
On Sat, Dec 29, 2007 at 06:03:15PM +0800, Erich Dollansky wrote:
I also do not know of any other CISC based design which made it to
mainstream.
VAX?
There is a working FreeBSD/VAX?
(Whatever - just as I don't understand any sane being run
On Sat, 29 Dec 2007 13:41:21 +0100 Erik Trulsson <[EMAIL PROTECTED]> wrote:
> On Sat, Dec 29, 2007 at 06:03:15PM +0800, Erich Dollansky wrote:
> > All RISC based designs need the alignment so that the CPU can fetch a CPU
> > word in one go. CISC based designs do not have this limitiation.
> >
> >
On Sat, Dec 29, 2007 at 06:03:15PM +0800, Erich Dollansky wrote:
> Hi,
>
> Kip Macy wrote:
>> Isn't it everything except x86?
>
> not really.
>
> All RISC based designs need the alignment so that the CPU can fetch a CPU
> word in one go. CISC based designs do not have this limitiation.
>
> I a
On Sat, Dec 29, 2007 at 06:03:15PM +0800, Erich Dollansky wrote:
> I also do not know of any other CISC based design which made it to
> mainstream.
VAX?
Joerg
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http://lists.freebsd.org/mailman/listinfo/freebs
On Sat, Dec 29, 2007 at 12:14:11AM -0800, Kip Macy wrote:
> Isn't it everything except x86?
>
> -Kip
x86 has the AC bit in the eflags. The AM bit in cr0 is enabled by the
kernel, and AC could be switched on by LD_PRELOADed shared object.
Last time I checked, our libc caused unaligned access in th
Hi,
Kip Macy wrote:
Isn't it everything except x86?
not really.
All RISC based designs need the alignment so that the CPU can fetch a
CPU word in one go. CISC based designs do not have this limitiation.
I also do not know of any other CISC based design which made it to
mainstream.
Erich
On Dec 7, 2007, at 6:43 PM, Ivan Voras wrote:
Hi,
Which of the architectures FreeBSD supports (if any) have strict
memory
alignment requirements? (in the sense that accessing a 32-bit integer
not aligned on a 32-bit address results in a hardware trap/exception).
ia64 and sparc64 at least.
Isn't it everything except x86?
-Kip
On Dec 29, 2007 12:11 AM, Erich Dollansky <[EMAIL PROTECTED]> wrote:
> Hi,
>
>
> Ivan Voras wrote:
> > Hi,
> >
> > Which of the architectures FreeBSD supports (if any) have strict memory
> > alignment requirements? (in the sense that accessing a 32-bit integer
Hi,
Ivan Voras wrote:
Hi,
Which of the architectures FreeBSD supports (if any) have strict memory
alignment requirements? (in the sense that accessing a 32-bit integer
not aligned on a 32-bit address results in a hardware trap/exception).
isn't this the case with SPARC and Itanium?
I know, t
Ivan Voras wrote:
Which of the architectures FreeBSD supports (if any) have strict memory
alignment requirements? (in the sense that accessing a 32-bit integer
not aligned on a 32-bit address results in a hardware trap/exception).
I believe ARM has such requirements (at least,
GCC for Arm does
Hi,
Which of the architectures FreeBSD supports (if any) have strict memory
alignment requirements? (in the sense that accessing a 32-bit integer
not aligned on a 32-bit address results in a hardware trap/exception).
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