On Wed, Jan 25, 2006 at 08:04:07AM -0700, Scott Long wrote:
> Either that, or the read imposes enough delay to let whatever was
> happening during the DELAY call work. I find it hard to believe that
> uncached writes would get delayed like this. I've lost the original
> posting on this, could yo
John Baldwin wrote:
On Tuesday 24 January 2006 19:34, Craig Boston wrote:
On Tue, Jan 24, 2006 at 10:43:49AM -0500, John Baldwin wrote:
What if you do a read of the lapic before the write? Maybe doing 'x =
lapic->eoi; lapic->eoi = 0;'?
Reading the lapic before the write has no effect.
Re
On Tuesday 24 January 2006 19:34, Craig Boston wrote:
> On Tue, Jan 24, 2006 at 10:43:49AM -0500, John Baldwin wrote:
> > What if you do a read of the lapic before the write? Maybe doing 'x =
> > lapic->eoi; lapic->eoi = 0;'?
>
> Reading the lapic before the write has no effect.
>
> Reading the l
On Tue, Jan 24, 2006 at 10:43:49AM -0500, John Baldwin wrote:
> What if you do a read of the lapic before the write? Maybe doing 'x =
> lapic->eoi; lapic->eoi = 0;'?
Reading the lapic before the write has no effect.
Reading the lapic after the write makes it work.
Craig
__
On Monday 23 January 2006 21:25, Craig Boston wrote:
> On Fri, Jan 20, 2006 at 03:42:21PM -0500, John Baldwin wrote:
> > On Thu, Jan 19, 2006 at 10:17:39PM -0700, Scott Long wrote:
> > > This points to a bus coherency problem. I wonder if your BIOS is
> > > incorrectly setting the memory region of
On Fri, Jan 20, 2006 at 03:42:21PM -0500, John Baldwin wrote:
> On Thu, Jan 19, 2006 at 10:17:39PM -0700, Scott Long wrote:
> > This points to a bus coherency problem. I wonder if your BIOS is
> > incorrectly setting the memory region of the apics as cachable. You'll
> > want to bug Baldwin about
On Friday 20 January 2006 16:26, Craig Boston wrote:
> On Fri, Jan 20, 2006 at 03:42:21PM -0500, John Baldwin wrote:
> > Hmm, well, you can actually try the PAT patch if you are feeling brave as
> > it maps all devices (including APICs) as uncacheable.
>
> Heh, took me a minute to find. I first fo
On Fri, Jan 20, 2006 at 03:42:21PM -0500, John Baldwin wrote:
> Hmm, well, you can actually try the PAT patch if you are feeling brave as it
> maps all devices (including APICs) as uncacheable.
Heh, took me a minute to find. I first found the one at
http://people.freebsd.org/~jhb/patches/pat.pat
On Friday 20 January 2006 10:27, Craig Boston wrote:
> On Thu, Jan 19, 2006 at 10:17:39PM -0700, Scott Long wrote:
> > This points to a bus coherency problem. I wonder if your BIOS is
> > incorrectly setting the memory region of the apics as cachable. You'll
> > want to bug Baldwin about this.
>
On Thu, Jan 19, 2006 at 10:17:39PM -0700, Scott Long wrote:
> This points to a bus coherency problem. I wonder if your BIOS is
> incorrectly setting the memory region of the apics as cachable. You'll
> want to bug Baldwin about this.
I CC-ed him on my post since he was working with me on the pro
Craig Boston wrote:
After trying everything I could think of to do to the I/O APIC code and
coming up empty, tonight I went back to the local APIC. I had
previously ruled it out since the lapic timer interrupt continued to
work fine even when the others stopped. However, adding some DELAY(1)
c
After trying everything I could think of to do to the I/O APIC code and
coming up empty, tonight I went back to the local APIC. I had
previously ruled it out since the lapic timer interrupt continued to
work fine even when the others stopped. However, adding some DELAY(1)
calls at key points caus
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