The solution is:
I have a function which pre-calculates the buffers required for processing
the packet. This is to eliminate any lack-of-memory errors during
processing.
In this function I loop over descriptors from next_to_check onwards. If I
loop over some descriptors with DD set and do not see
Hi Jack,
Thanks for the explanation. Do you suggest that I keep reading rx
descriptor with DD bit and keep them pending till I get the descriptor with
EOP set ? How much max delay can be expected for the EOP descriptor to be
written back ?
Regards,
Kaushal
On Sun, Jul 7, 2013 at 10:40 PM, Jack V
The "potential race condition" as the data sheet puts it, is only when you
are
trying to manage your RX ring by reading the RDH register, this is a bad
idea
anyway, none of our (Intel) drivers do this. Using the DD bit is what you
want
to do. The DD bit is set when the descriptor is written back, a
In 82599, for a Jumbo packet of 9.5 K ( which consumes 5 descriptors of
2048 bytes each ), when does the Descriptor write back happen ? Does it
happen per Descriptor or once per aggregated Descriptors ? Is it possible
that all descriptors except last one to be written back and when you read
RDH reg
