Hans Petter Selasky wrote:
On Wednesday 05 August 2009 15:17:18 Grzegorz Bernacki wrote:
I will do some more testing and then commit it to USB P4.
Hi Hans,
Have you had a chance to perform your tests? Do you see any problems on
your machine after applying the patch?
regards,
Grzesiek
_
On Wednesday 05 August 2009 15:17:18 Grzegorz Bernacki wrote:
> Below is the patch with that solution. I tested it on ARM and PowerPC
> and it fixes the problem. Please test it on other platforms you have to
> see if there is no regression.
Hi,
Your patch look Ok.
I will do some more testing and
Hans Petter Selasky wrote:
There are two kinds of DMA memory in USB regard:
1) Transfer descriptors are allocated in coherent DMA memory.
Operation logic:
1.a) Write to descriptor.
1.b.0) Call usb_pc_cpu_flush() to write data to RAM.
1.b.1) Write more fields to descriptor.
1.b.2) Call usb_pc_
On Tuesday 04 August 2009 16:41:36 Grzegorz Bernacki wrote:
> Hans Petter Selasky wrote:
> > CC'ed current: We have a case on ARM where bus_dmamap_sync() is not
> > suffient to update the CPU cache. One reason for this is that USB needs
> > to invalidate the same memory area multiple times. Busdma
Hans Petter Selasky wrote:
CC'ed current: We have a case on ARM where bus_dmamap_sync() is not suffient
to update the CPU cache. One reason for this is that USB needs to invalidate
the same memory area multiple times. Busdma sync expects paired operation when
using the PRE and POST flags, fro
On 2009-08-03, at 17:59, Hans Petter Selasky wrote:
On Monday 03 August 2009 17:01:37 Rafal Jaworowski wrote:
Hans,
So how do you want to proceed with these cache sync issues? We need
to
fix this before 8.0.
Hi,
CC'ed current: We have a case on ARM where bus_dmamap_sync() is not
suffie
On Monday 03 August 2009 17:01:37 Rafal Jaworowski wrote:
> Hans,
> So how do you want to proceed with these cache sync issues? We need to
> fix this before 8.0.
Hi,
CC'ed current: We have a case on ARM where bus_dmamap_sync() is not suffient
to update the CPU cache. One reason for this is tha
On 2009-07-25, at 05:34, M. Warner Losh wrote:
In message: <200907232209.47729.hsela...@c2i.net>
Hans Petter Selasky writes:
: On Thursday 23 July 2009 20:53:06 Marcel Moolenaar wrote:
: > All,
: >
: > I went over the thread and this is what I have to say about it:
: >
: > Using bus
In message: <200907232209.47729.hsela...@c2i.net>
Hans Petter Selasky writes:
: On Thursday 23 July 2009 20:53:06 Marcel Moolenaar wrote:
: > All,
: >
: > I went over the thread and this is what I have to say about it:
: >
: > Using busdma to manage/control CPU caches is wrong for the
On Thursday 23 July 2009 20:53:06 Marcel Moolenaar wrote:
> All,
>
> I went over the thread and this is what I have to say about it:
>
> Using busdma to manage/control CPU caches is wrong for the
> following simple reason: bus_dmamap_sync() has the side-effect
> of copying to and from the bounce bu
All,
I went over the thread and this is what I have to say about it:
Using busdma to manage/control CPU caches is wrong for the
following simple reason: bus_dmamap_sync() has the side-effect
of copying to and from the bounce buffer (if applicable).
CPU caches should be kept coherent by using an
11 matches
Mail list logo
