I have seen logic analysers that claim to get a sample rate up to 1 MHz
from the parallel port depending on hardware.
https://jwasys.home.xs4all.nl/old/diy2.html
If I remember correctly, isn't there a 18.5 Hz interrupt/clock as standard
on the pc? Might be useful to know for original poster.
Den
On 12/31/18 8:14 PM, Tom Ehlert wrote:
I thought about having an ISR capturing the data being called at capture
rate, which should be something around 100kHz to 150kHz
unlikely. expect *each* inp()/outp() operation to use O(500ns)
there is also a notable delay between applying an input 0/1 vo
