From: Mitchel Humpherys
The pgtbl_cfg object has a few handy properties that we'd like to make
use of later (returning the pgd in a domain attribute, for example).
Keep track of the domain pgtbl_cfg in the domain structure.
Signed-off-by: Mitchel Humpherys
---
drivers/iommu/arm-smmu.c | 11 +++
Allow a SMMU device to opt into allocating a TTBR1 pagetable.
The size of the TTBR1 region will be the same as
the TTBR0 size with the sign extension bit set on the highest
bit in the region unless the upstream size is 49 bits and then
the sign-extension bit will be set on the 49th bit.
The map/u
From: Jeremy Gebben
Add support to return the value of the TTBR0 register in response
to a request via DOMAIN_ATTR_TTBR0.
Signed-off-by: Jeremy Gebben
Signed-off-by: Jordan Crouse
---
drivers/iommu/arm-smmu.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/iommu/arm
Pursuant to the arm-smmu-v3 SVM support:
https://lists.linuxfoundation.org/pipermail/iommu/2017-February/020599.html
I felt it would be helpful if I would demonstrate how Qualcomm implements
per-process pagetables for several generations of SoCs and GPUs focusing on the
Adreno A540 GPU and an arm
Implement support for dynamic domain switching. This feature is
only enabled when the qcom,dynamic device tree attribute for an smmu
instance.
In order to use dynamic domains, a non-dynamic domain must first
be created and attached. The non-dynamic domain must remain
attached while the device is
Add an API to create a dynamic domain from an existing domain.
A dynamic domain is a special IOMMU domain that is attached to
the same device as the parent domain but is backed by separate
pagetables. Devices such as GPUs that support asynchronous
methods for switching pagetables can create dynamic
Add a new domain attribute to enable the TTBR1 pagetable for drivers
and devices that support it. This will enabled using a TTBR1 (otherwise
known as a "global" or "system" pagetable for devices that support a split
pagetable scheme for switching pagetables quickly and safely.
Signed-off-by: Jord
From: Jeremy Gebben
In the ARM SMMU architecture, pagetable programming is controlled
by the TTBR0 register. The layout of this
registers varies depending on the pagetable format in use.
In particular, the ASID (address space ID) field is found in
CONTEXTIDR when using V7S format and in the top b
Instead of checking for a5xx_gpu->gpmu_iova during destroy we
accidently check a5xx_gpu->gpmu_bo.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
b/drivers/gpu/dr
The interrupt status was being cleared before processing the handlers.
a5xx_rbbm_err_irq() was checking the interrupt status again, which would
likely turn out bad because the interrupt status would be 0 (or at least
different). Pass the original status to the function instead.
Also, skip clearing
Hey Rob, here are a handful of things that might be fixable for 4.11 but if not
consider them for -next.
Jordan
Jordan Crouse (4):
drm/msm: Fix wrong pointer check in a5xx_destroy
drm/msm: Don't increase priv->num_aspaces until we know that it fits
drm/msm: Pass interrupt status to a5xx_rbb
priv->num_aspaces is increased and then checked to see if it still fits
in the priv->aspace array. If it doesn't, we warn and exit but
priv->num_aspaces remains incremented.
Don't incremement the count until we know that it fits in the array.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/ms
Output the upper 32 bits of a 64 bit iova in the RD_CMDSTREAM_ADDR
section while maintaining backwards compatibility for tools that
only understand 32 bit iovas.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_rd.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/
memptrs->wptr seems to be unused. Remove it to avoid
confusing the upcoming preemption code.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 ---
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 -
2 files changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a
There isn't any generic code that uses ->idle so remove it.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 4 ++--
drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 4 ++--
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 9 -
drivers/gpu/drm/msm/adreno/a5xx_gpu.h | 1 +
d
Here is v2 of the preemption series - Changes:
* Refactored API in DRM_IOCTL_MSM_GEM_INFO (Thanks Emil Velikov)
* Removed preemption worker and fixed atomics (Thanks Stephen Boyd)
* Various fixes and improvements based on testing
Thanks!
Jordan
Jordan Crouse (11):
drm/msm: Make sure to deta
We should be detaching the MMU before destroying the address
space. To do this cleanly, the detach has to happen in
adreno_gpu_cleanup() because it needs access to structs
in adreno_gpu.c. Plus it is better symmetry to have
the attach and detach at the same code level.
Signed-off-by: Jordan Crous
In the future we won't have a fixed set of addresses spaces.
Instead of going through the effort of assigning a ID for each
address space just use the address space itself as a token for
getting / putting an iova.
This forces a few changes in the gem object however: instead
of using a simple index
Simply the code, use snprintf correct and make sure that we memset
the rest of the segment if the memory size in the ELF file is larger
than the file size.
Signed-off-by: Jordan Crouse
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 +-
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 70 +
Add the infrastructure to support the idea of multiple ringbuffers.
Assign each ringbuffer an id and use that as an index for the various
ring specific operations.
The biggest delta is to support legacy fences. Each fence gets its own
sequence number but the legacy functions expect to use a unique
Modify the 'pad' member of struct drm_msm_gem_info to 'hint'. If the
user sets 'hint' to non-zero it means that they want a IOVA for the
GEM object instead of a mmap() offset. Return the iova in the 'offset'
member.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_drv.c | 23
The amount of information that we need to pass into msm_gpu_init()
is steadily increasing, so add a new struct to stabilize the function
call and make it easier to add new configuration down the line.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 12 ++--
dri
Add a shadow pointer to track the current command being written into
the ring. Don't commit it as 'cur' until the command is submitted.
Because 'cur' is used to construct the software copy of the wptr this
ensures that somebody peeking in on the ring doesn't assume that a
command is inflight while
We use a global ringbuffer size and block size for all targets and
at least for 5XX preemption we need to know the value the RB_CNTL
in several locations so it makes sense to caculate it once and use
it everywhere.
The only monkey wrench is that we need to disable the RPTR shadow
for A430 targets
Implement preemption for A5XX targets - this allows multiple
ringbuffers for different priorities with automatic preemption
of a lower priority ringbuffer if a higher one is ready.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/Makefile | 1 +
drivers/gpu/drm/msm/adreno/a5xx
There are reasons for a memory object to outlive the file descriptor
that created it and so the address space that a buffer object is
attached to must also outlive the file descriptor. Reference count
the address space so that it can remain viable until all the objects
have released their addresses
User space needs to know where the GMEM whole starts so that they
can set up the addressing correctly.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 +++
include/uapi/drm/msm_drm.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/m
Zero sized buffer objects tend to make various bits of the GEM
infrastructure complain:
WARNING: CPU: 1 PID: 2323 at drivers/gpu/drm/drm_mm.c:389
drm_mm_insert_node_generic+0x258/0x2f0
Modules linked in:
CPU: 1 PID: 2323 Comm: drm-api-test Tainted: GW
4.9.0-rc4-00906-g693af44 #213
H
Hey Rob - here are a handful of new features and more extensive bug fixes that
might be suitable for 4.12.
Of note is the reference count for address spaces which is a pre-requisite for
per-instance pagetables and the move to OPP tables which is a stepping stone for
all sorts of clock related shen
Some A3XX and A4XX GPU targets required that the GPU clock be
programmed to a non zero value when it was disabled so
27Mhz was chosen as the "invalid" frequency.
Even though newer targets do not have the same clock restrictions
we still write 27Mhz on clock disable and expect the clock subsystem
t
If a OPP table is defined for the GPU device in the device tree use
that in lieu of the downstream style GPU frequency table. If we do
use the downstream table convert it to a OPP table so that we can
take advantage of the OPP lookup facilities later.
Signed-off-by: Jordan Crouse
---
drivers/gpu
Instead of using a fixed list of clock names use the clock-names
list in the device tree to discover and get the list of clocks
that we need.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_gpu.c | 76 ++-
drivers/gpu/drm/msm/msm_gpu.h | 4 ++-
2
Since we have the infrastructure for IOMMU function tables it makes
sense to use it to differentiate between v1 and v2 targets. It adds
a bit more infrastructure but it also gives us the freedom to expand
on each flavor (especially v2) for things like dynamic domains.
Signed-off-by: Jordan Crouse
Pass the index of the MMU domain in struct msm_file_private instead
of assuming gpu->id throughout the submit path.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_drv.c| 2 ++
drivers/gpu/drm/msm/msm_drv.h| 6 +-
drivers/gpu/drm/msm/msm_gem.h| 1 +
driver
Using the framework described here
https://lists.linuxfoundation.org/pipermail/iommu/2017-March/020716.html
This implements per-instance pagetables for the GPU driver creating an
individual pagetable for each file descriptor (so not strictly per-process
but in practice we can't share buffers betw
Dynamic IOMMU domains allow multiple pagetables to be attached to the
same IOMMU device. These can be used by smart devices like the GPU
that can switch the pagetable dynamically between DRM instances.
Add support for dynamic IOMMU domains if they are enabled and
supported by your friendly neighbo
A5XX GPUs can be run in either 32 or 64 bit mode. The GPU registers
and the microcode use 64 bit virtual addressing in either case but the
upper 32 bits are ignored if the GPU is in 32 bit mode. There is no
performance disadvantage to remaining in 64 bit mode even if we are
only generating 32 bit a
Use a TTBR1 pagetable for the GPU IOMMU domain and map all
the GPU kernel side buffer objects into that range. This
will make it easier to switch out TTBR0 for per-process
pagetables.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 18 --
drivers/gpu/d
Support per-instance pagetables for 5XX targets. Per-instance
pagetables allow each open DRM instance to have its own VM memory
space to prevent accidently or maliciously copying or overwriting
buffers from other instances. It also opens the door for SVM since
any given CPU side address can be more
On Tue, Mar 07, 2017 at 09:39:48AM -0700, Jordan Crouse wrote:
> Pursuant to the arm-smmu-v3 SVM support:
>
> https://lists.linuxfoundation.org/pipermail/iommu/2017-February/020599.html
>
> I felt it would be helpful if I would demonstrate how Qualcomm implements
> per-process pagetables for seve
On Tue, Mar 07, 2017 at 06:11:38PM +, Mark Rutland wrote:
> On Tue, Mar 07, 2017 at 09:39:55AM -0700, Jordan Crouse wrote:
> > Implement support for dynamic domain switching. This feature is
> > only enabled when the qcom,dynamic device tree attribute for an smmu
> > instance.
> >
> > In order
On Tue, Mar 07, 2017 at 10:14:14AM -0700, Jordan Crouse wrote:
> Using the framework described here
>
> https://lists.linuxfoundation.org/pipermail/iommu/2017-March/020716.html
>
> This implements per-instance pagetables for the GPU driver creating an
> individual pagetable for each file descript
On Tue, Mar 07, 2017 at 10:14:20AM -0700, Jordan Crouse wrote:
> Support per-instance pagetables for 5XX targets. Per-instance
> pagetables allow each open DRM instance to have its own VM memory
> space to prevent accidently or maliciously copying or overwriting
> buffers from other instances. It a
On Tue, Mar 07, 2017 at 09:39:55AM -0700, Jordan Crouse wrote:
> Implement support for dynamic domain switching. This feature is
> only enabled when the qcom,dynamic device tree attribute for an smmu
> instance.
>
> In order to use dynamic domains, a non-dynamic domain must first
> be created and
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