On Wed, Jun 27, 2018 at 03:27:35PM +0530, Sandeep Panda wrote:
> Document the bindings used for the sn65dsi86 DSI to eDP bridge.
>
> Changes in v1:
> - Rephrase the dt-binding descriptions to be more inline with existing
>bindings (Andrzej Hajda).
> - Add missing dt-binding that are parsed
Unlike other compositors, we don't get a crtc disable from weston
when the cable is unplugged. As such, when the cable is re-plugged
the kernel doesn't detect an enable/mode change and initiates a
simple plane update instead of a modeset.
This patch clears the mode when all planes are off.
On 2018-06-29 02:23, Sean Paul wrote:
QC bus scaling isn't upstream yet, so remove the bus scaling code until
it is.
Hi Sean,
MDP5 driver does have bus_scaling code under
DOWNSTREAM_CONFIG_MSM_BUS_SCALING gate.
On similar lines we kept the DPU bus_scaling code under the
In commits:
34a2ab5e0689 ("drm: Add acquire ctx parameter to ->update_plane")
1931529448bc ("drm: Add acquire ctx parameter to ->plane_disable")
a pointer to a drm_modeset_acquire_ctx structure was added as an
argument to the method prototypes. The transitional helpers are
supposed to be
> @@ -91,12 +93,13 @@ static int zap_shader_load_mdt(struct msm_gpu *gpu,
> const char *fwname)
> ret = qcom_mdt_load(dev, fw, fwname, GPU_PAS_ID,
> mem_region, mem_phys, mem_size, NULL);
> } else {
> - char newname[strlen("qcom/") +
