On 2018-10-05 18:49, YueHaibing wrote:
Remove duplicated include.
Signed-off-by: YueHaibing
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
b/drivers/gpu/drm/msm/disp/dpu1/d
PM resume was crashing during dpu_kms_pm_resume. This patch removes
dpu_kms_pm_suspend/resume so that msm_pm_suspend/resume uses the atomic
helpers instead (see next patch). This patch also removes
dpu_kms_is_suspend_blocked since it is never called.
v2: Reorganized patches in patchset
Signed-off
Since drm core's modeset locks serialize atomic commits, we don't need to
track whether or not we're in a suspended state from inside the crtc for
dpu_crtc_enable/disable. This patch removes the suspend logic from the crtc and
removes the relevant tracing from dpu_trace. Since we removed all calls
Removes the traces of the non-atomic helper calls in
msm_pm_suspend/resume since we just deleted those functions (see patch
1). Also removes the drm_kms_helper_poll_disable/enable calls, since
the DRM_CONNECTOR_POLL_CONNECT flag is never set so periodic polling
doesn't happen anyways.
v2: reorgani
Since we removed all suspend logic from the crtc code (see patch 3/4),
dpu_crtc_reset does the same things as drm_atomic_helper_crtc_reset, so let's
just replace it with a call to the atomic helper.
v3: added patch to patchset
Signed-off-by: Bruce Wang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc
Patches 1-2: Changes msm_pm_resume implementation to use atomic helpers
and
removes the previously used dpu_kms_pm_suspend/resume functions.
Patches 3-4: Removes reliance on knowledge about suspend state from crtc
and removes dpu_crtc_reset in favour of the atomic helper.
v2: Reorganized patch ord
On 2018-10-05 12:49, Jeykumar Sankaran wrote:
While creating display and event threads per crtc, validate
them before setting their priorities.
Change-Id: I1dda805286df981c0f0e2b26507d089d3a21ff6c
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/msm_drv.c | 49
++--
The CP performance counter selects were accidentally marked as protected
so they couldn't be written from PM4 streams. Remove the protection
because user space does have an interest in setting up their own
counters.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 4 +---
While creating display and event threads per crtc, validate
them before setting their priorities.
Change-Id: I1dda805286df981c0f0e2b26507d089d3a21ff6c
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/msm_drv.c | 49 ++-
1 file changed, 16 insertion
On Fri, Oct 05, 2018 at 11:48:43AM -0400, Bruce Wang wrote:
> The suspend_state field is no longer used and can be removed along with
> dpu_kms_is_suspend_state.
>
This can be rolled up into patch 3, since that's where the usage of these is
being removed.
Sean
> Signed-off-by: Bruce Wang
> ---
On Fri, Oct 05, 2018 at 11:48:42AM -0400, Bruce Wang wrote:
> dpu_crtc_enable/disable/reset are only being called upon
> initialization/destruction of the device and as part of the PM
> suspend/resume handling.
*and dpms/enable on/off
> Since core suspend and resume calls
> are guarenteed to not
On Fri, Oct 05, 2018 at 01:27:54PM -0400, Sean Paul wrote:
> On Fri, Oct 05, 2018 at 11:48:40AM -0400, Bruce Wang wrote:
> > PM resume was crashing during dpu_kms_pm_resume. This patch removes
> > dpu_kms_pm_suspend/resume so that msm_pm_suspend/resume uses the atomic
> > helpers instead (see next
On Fri, Oct 05, 2018 at 11:48:41AM -0400, Bruce Wang wrote:
> Removes the traces of the non-atomic helper calls in
> msm_pm_suspend/resume since we just deleted those functions (see patch
> 1). Also removes the drm_kms_helper_poll_disable/enable calls, since
> the DRM_CONNECTOR_POLL_CONNECT flag is
On Fri, Oct 05, 2018 at 11:48:40AM -0400, Bruce Wang wrote:
> PM resume was crashing during dpu_kms_pm_resume. This patch removes
> dpu_kms_pm_suspend/resume so that msm_pm_suspend/resume uses the atomic
> helpers instead (see next patch). This patch also removes
> dpu_kms_is_suspend_blocked since
On Fri, Oct 05, 2018 at 12:06:06PM +0530, Sharat Masetty wrote:
>
>
> On 8/27/2018 8:41 PM, Jordan Crouse wrote:
> >Add dev_pm_opp_get_interconnect_bw() to read the interconnect
> >bandwidth values for a given OPP.
> >
> >Signed-off-by: Jordan Crouse
> >---
> > drivers/opp/of.c | 36 +
dpu_crtc_enable/disable/reset are only being called upon
initialization/destruction of the device and as part of the PM
suspend/resume handling. Since core suspend and resume calls
are guarenteed to not overlap with one another we don't need to
track whether or not we're in a suspended state from i
Patches 1-2: Changes msm_pm_resume implementation to use atomic helpers and
removes the previously used dpu_kms_pm_suspend/resume functions.
Patches 3-4: Removes reliance on knowledge about suspend state from crtc
Bruce Wang (4):
drm/msm/dpu: Remove dpu_kms_pm_suspend/resume
drm/msm: Cut dpu_k
The suspend_state field is no longer used and can be removed along with
dpu_kms_is_suspend_state.
Signed-off-by: Bruce Wang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 16
1 file changed, 16 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
b/drivers/gpu/drm/
Removes the traces of the non-atomic helper calls in
msm_pm_suspend/resume since we just deleted those functions (see patch
1). Also removes the drm_kms_helper_poll_disable/enable calls, since
the DRM_CONNECTOR_POLL_CONNECT flag is never set so periodic polling
doesn't happen anyways.
Signed-off-b
PM resume was crashing during dpu_kms_pm_resume. This patch removes
dpu_kms_pm_suspend/resume so that msm_pm_suspend/resume uses the atomic
helpers instead (see next patch). This patch also removes
dpu_kms_is_suspend_blocked since it is never called.
Signed-off-by: Bruce Wang
---
drivers/gpu/drm
On Fri, Oct 05, 2018 at 06:38:35PM +0530, Sharat Masetty wrote:
> The last level system cache can be partitioned to 32 different slices
> of which GPU has two slices preallocated. One slice is used for caching GPU
> buffers and the other slice is used for caching the GPU SMMU pagetables.
> This pat
On Fri, Oct 05, 2018 at 06:38:32PM +0530, Sharat Masetty wrote:
> Add the registers needed for configuring the system cache slice info and
> other parameters in the GPU.
This would conflict with msm-next or at least with the latest update from the
rnndb. It is good to have this out here for people
The last level system cache can be partitioned to 32 different slices
of which GPU has two slices preallocated. One slice is used for caching GPU
buffers and the other slice is used for caching the GPU SMMU pagetables.
This patch talks to the core system cache driver to acquire the slice handles,
c
Allow different Adreno targets the ability to pass
specific mmu features to the generic layers. This will
help conditionally configure certain iommu features for
certain Adreno targets.
Also Add a few simple support functions to support a bitmask of
features that a specific MMU implementation supp
This patch adds a register range in the gpu CX domain. This is needed to
support the last level system cache(LLC).
Signed-off-by: Sharat Masetty
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
From: Vivek Gautam
Qualcomm SoCs have an additional level of cache called as
System cache or Last level cache[1]. This cache sits right
before the DDR, and is tightly coupled with the memory
controller.
The cache is available to all the clients present in the
SoC system. The clients request their
The register read-modify-write construct is generic enough
that it can be used by other subsystems as needed, create
a more generic rmw() function and have the gpu_rmw() use
this new function.
Signed-off-by: Sharat Masetty
Reviewed-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_drv.c | 8 +++
Add the registers needed for configuring the system cache slice info and
other parameters in the GPU.
Signed-off-by: Sharat Masetty
---
drivers/gpu/drm/msm/adreno/a6xx.xml.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx.xml.h
b/drivers/gpu/drm/msm/adreno
From: Jordan Crouse
llcc_slice_getd can return a ERR_PTR code on failure. Add a IS_ERR_OR_NULL
check to subsequent API calls that use struct llcc_slice_desc to guard
against faults and to let the leaf drivers get away with safely using a
ERR_PTR() encoded "pointer" in the aftermath of a llcc_slic
Some hardware variants contain a system level cache or the last level
cache(llc). This cache is typically a large block which is shared by multiple
clients on the SOC. GPU uses the system cache to cache both the GPU data
buffers(like textures) as well the SMMU pagetables. This helps with
improved r
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