Move and maintain RM initialization flag checks
from KMS to RM.
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 6 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 12
RM was using encoder id's to tag HW block's to reserve
and retrieve later for display pipeline. Now
that all the reserved HW blocks for a display are
maintained in its crtc state, no retrieval is needed.
This patch cleans up RM of encoder id tagging.
Signed-off-by: Jeykumar Sankaran
---
Replacing with simpler linked list helper iterators.
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 120 +
1 file changed, 46 insertions(+), 74 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
Since HW reservations are happening through atomic_check
and all the display commits are catered by a single commit thread,
it is not necessary to protect the interfaces by a separate
mutex.
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 24
we don't have enough reasons why the HW block looping's
cannot happen in the same function. So merge them.
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 63 ++
1 file changed, 26 insertions(+), 37 deletions(-)
diff --git
Get rid of hw block pointer in RM iter as we can
access the same through dpu_hw_blk.
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 10 ++
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
This flag was introduced as a fix to notify modeset complete
when hw reservations were happening in both atomic_check
and atomic_commit paths. Now that we are reserving only in
atomic_check, we can get rid of this flag.
Signed-off-by: Jeykumar Sankaran
---
Validate layer mixer pairs for compatibility before retrieving
the connected pingpong blocks.
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 61 ++
1 file changed, 17 insertions(+), 44 deletions(-)
diff --git
msm_display_topology was used for providing HW block
layout of the pipeline for a specific display topology.
We already got rid of its usage from DSI driver. In DPU,
it was used to provide the details on HW blocks while
reserving resources. Since we can use the crtc state used
for storing the
Instead of letting encoder make a centralized reservation for
all of its display DRM components, this path splits the
responsibility between CRTC and Encoder, each requesting
RM for the HW mapping of its own domain.
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
We cleaned up RM reserve api's enough to get rid of
most of its unwanted checks and release handlers. To
improve further the readability of the function, merging
down the individual HW type allocators into one function.
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
Encoder uses test_only flag to differentiate RM reservations
invoked from atomic check and atomic_commit phases.
After reserving the HW blocks, if test_only was set, RM
releases the reservation. Retains them if not. Since we
got rid of RM reserve call from atomic_commit path, get rid
of this flag.
hw_mdp block is common for displays. No need
to reserve per display.
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 7 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 20
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 10 --
3 files
Not used. Remove from RM.
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 3 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 7 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 6 +-
3 files changed, 4 insertions(+), 12 deletions(-)
diff --git
Unused variable in the driver.
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 12
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 2 --
2 files changed, 14 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
Definition was removed already. Clean up header declaration.
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 8
1 file changed, 8 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
index
RM was equipped with reservation tracking structure RSVP
to cache HW reservation of displays for certain clients
where atomic_checks (atomic commit with TEST_ONLY) for all
the displays are called before their respective atomic_commits.
Since DPU doesn't support the sequence anymore, clean up
the
struct dpu_hw_blk has hw block type info. Remove duplicate
type tracking in struct dpu_rm_hw_blk.
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 17 -
1 file changed, 4 insertions(+), 13 deletions(-)
diff --git
Layer mixer/pingpong block counts and hw ctl block counts
will not be same for all the topologies (e.g. layer
mixer muxing to single interface)
Use the encoder's split_role info to retrieve the
respective control path for programming.
Signed-off-by: Jeykumar Sankaran
---
Not actively used. Clean up the crtc mixer struct.
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 2 --
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 2 --
2 files changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
Usage of hw block iterators are only RM internal. Instead
of using generic void pointers for HW blocks, use dpu
specific structure. It helps us to get rid of duplicate
hw block id's maintained in RM wrapper.
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 27
HW blocks reserved for a display are stored in crtc state.
No one outside RM is interested in using these API's for
HW block list iterations.
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 37 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 46
Submitting series of patches to clean up DPU resource manager (RM)
of complicated hw iterations, redundant data maintenence and eventually
modifying the DPU to reserve display HW blocks only in atomic check
and caching the assigned HW blocks in atomic CRTC state.
Thanks,
Jeykumar S.
Jeykumar
DPU maintained reservation lists to cache assigned
HW blocks for the display and a retrieval mechanism for
the individual DRM components to query their respective
HW blocks.
This patch uses the sub-classed CRTC state to store
and track HW blocks assigned for different components
of the display
Use the hw block pointers stored in crtc state to
release them back to RM resource pool. This change
is made to uncouple RM reservation from encoder_id.
Separate change is submitted to clean up RM of
encoder id tagging.
Signed-off-by: Jeykumar Sankaran
---
On 2018-10-03 13:22, Sean Paul wrote:
From: Sean Paul
Similar to the atomic helpers, we should enable vblank while we're
waiting for the commit to finish. DPU needs this, MDP5 seems to work
fine without it.
Signed-off-by: Sean Paul
---
As such I dont see any issue with this patch but I have
While creating display and event threads per crtc, validate
them before setting their priorities.
changes in v2:
- use dev_warn (Abhinav Kumar)
changes in v3:
- fix compilation error
Change-Id: I1dda805286df981c0f0e2b26507d089d3a21ff6c
Signed-off-by: Jeykumar Sankaran
---
While creating display and event threads per crtc, validate
them before setting their priorities.
changes in v2:
- use dev_warn (Abhinav Kumar)
Change-Id: I1dda805286df981c0f0e2b26507d089d3a21ff6c
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/msm_drv.c | 49
On 2018-10-08 15:24, Jeykumar Sankaran wrote:
On 2018-09-20 07:58, Sean Paul wrote:
From: Sean Paul
I noticed an empty label while driving by and decided to use
coccinelle to see if there were any more. Here's the spatch and the
invocation:
---
@@
identifier lbl;
expression E;
@@
- goto
On 2018-09-20 07:58, Sean Paul wrote:
From: Sean Paul
Per chapter 15 of coding-style, removing 'inline' keyword from
functions
that are larger than a typical macro. In a couple of cases I've
simplified the function and kept the inline.
Signed-off-by: Sean Paul
Reviewed-by: Jeykumar
On 2018-09-20 07:58, Sean Paul wrote:
From: Sean Paul
These functions aren't used anywhere, remove them.
Signed-off-by: Sean Paul
Reviewed-by: Jeykumar Sankaran
---
.../gpu/drm/msm/disp/dpu1/msm_media_info.h| 171 --
1 file changed, 171 deletions(-)
diff --git
On 2018-09-20 07:58, Sean Paul wrote:
From: Sean Paul
Local variable is not needed and condition can't be hit.
Signed-off-by: Sean Paul
Reviewed-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff
On 2018-09-20 07:58, Sean Paul wrote:
From: Sean Paul
We call out of the virt encoder into phys only to call back into the
virt for hw reset. So remove the indirection and just call the virt
function directly.
Signed-off-by: Sean Paul
Reviewed-by: Jeykumar Sankaran
---
On 2018-09-20 07:58, Sean Paul wrote:
From: Sean Paul
I noticed an empty label while driving by and decided to use
coccinelle to see if there were any more. Here's the spatch and the
invocation:
---
@@
identifier lbl;
expression E;
@@
- goto lbl;
+ return E;
...
- lbl:
return E;
@@
From: Sean Paul
This patch uses the proper do_div() macro to perform u64 division and
guards against overflow if the result is too large for the unsigned long
return type
Fixes: a2c3c0a54d4c drm/msm/a6xx: Add devfreq support for a6xx
Cc: Sharat Masetty
Signed-off-by: Sean Paul
---
From: Sean Paul
A small fixup I posted with my v2 patch [1] that was dropped.
[1]- https://lists.freedesktop.org/archives/freedreno/2018-October/003647.html
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff
On Fri, Oct 05, 2018 at 05:04:03PM -0400, Bruce Wang wrote:
> Since we removed all suspend logic from the crtc code (see patch 3/4),
> dpu_crtc_reset does the same things as drm_atomic_helper_crtc_reset, so let's
> just replace it with a call to the atomic helper.
>
> v3: added patch to patchset
On Fri, Oct 05, 2018 at 05:04:02PM -0400, Bruce Wang wrote:
> Since drm core's modeset locks serialize atomic commits, we don't need to
> track whether or not we're in a suspended state from inside the crtc for
> dpu_crtc_enable/disable. This patch removes the suspend logic from the crtc
> and
>
On Fri, Oct 05, 2018 at 05:04:01PM -0400, Bruce Wang wrote:
> Removes the traces of the non-atomic helper calls in
> msm_pm_suspend/resume since we just deleted those functions (see patch
> 1). Also removes the drm_kms_helper_poll_disable/enable calls, since
> the DRM_CONNECTOR_POLL_CONNECT flag
On Mon, Oct 08, 2018 at 02:57:29PM +0530, Sravanthi Kollukuduru wrote:
> The interconnect framework is designed to provide a
> standard kernel interface to control the settings of
> the interconnects on a SoC.
>
> The interconnect API uses a consumer/provider-based model,
> where the providers
On Mon, Oct 08, 2018 at 07:29:03PM +0530, Sharat Masetty wrote:
>
>
> On 10/5/2018 8:37 PM, Jordan Crouse wrote:
> >On Fri, Oct 05, 2018 at 06:38:35PM +0530, Sharat Masetty wrote:
> >>The last level system cache can be partitioned to 32 different slices
> >>of which GPU has two slices
On 10/5/2018 8:37 PM, Jordan Crouse wrote:
On Fri, Oct 05, 2018 at 06:38:35PM +0530, Sharat Masetty wrote:
The last level system cache can be partitioned to 32 different slices
of which GPU has two slices preallocated. One slice is used for caching GPU
buffers and the other slice is used for
On 10/5/2018 8:31 PM, Jordan Crouse wrote:
On Fri, Oct 05, 2018 at 06:38:32PM +0530, Sharat Masetty wrote:
Add the registers needed for configuring the system cache slice info and
other parameters in the GPU.
This would conflict with msm-next or at least with the latest update from the
Add a few additional registers in the CX domain needed to implement
system cache support for a6xx.
---
rnndb/adreno/a6xx.xml | 5 +
1 file changed, 5 insertions(+)
diff --git a/rnndb/adreno/a6xx.xml b/rnndb/adreno/a6xx.xml
index b2bd64b..78ba1ce 100644
--- a/rnndb/adreno/a6xx.xml
+++
Add interconnect properties such as interconnect provider specifier
, the edge source and destination ports which are required by the
interconnect API to configure interconnect path for MDSS.
Signed-off-by: Sravanthi Kollukuduru
---
Documentation/devicetree/bindings/display/msm/dpu.txt | 8
The interconnect API provides an interface for consumer drivers to express
their bandwidth needs in the SoC. This data is aggregated and the on-chip
interconnect hardware is configured to the appropriate power/performance
profile.
MDSS is one of the interconnect consumers which uses the
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