On Fri, Jan 25, 2019 at 10:48 AM Eduardo Lima Mitev wrote:
>
> There are a bunch of instructions emitted on ir3_compiler_nir related to
> offset computations for IO opcodes (ssbo, image, etc). This small series
> explores the possibility of moving these instructions to NIR, where we
> have higher
Eduardo Lima Mitev writes:
> ir3 compiler has an integer multiply-add instruction (IMAD_S24)
> that is used for different offset calculations in the backend.
> Since we intend to move some of these calculations to NIR, we need
> a new ALU op that can represent it.
> ---
>
Eduardo Lima Mitev writes:
> This is an internal intrinsic intended to be injected by a
> (freedreno-specific) 'lower_sampler_io' pass that will be introduced
> later in this series; and consumed by ir3_compiler_nir.
>
> The intrinsic will load in SSA values for various constants
> for images
The specification in NIR has to be exact. Otherwise it will
constant-fold in a way that doesn't reflect what the hardware would
do, leading to subtle bugs.
On Fri, Jan 25, 2019 at 11:06 AM Eduardo Lima Mitev wrote:
>
> On 1/25/19 5:01 PM, Ilia Mirkin wrote:
> > On Fri, Jan 25, 2019 at 10:58 AM
On 1/25/19 5:01 PM, Ilia Mirkin wrote:
> On Fri, Jan 25, 2019 at 10:58 AM Ilia Mirkin wrote:
>>
>> IMAD_S24 isn't src0 * src1 + src2 though. I think this could be called
>> imad24, which I suspect exits on many GPUs (nv50-era NVIDIA definitely
>> had this, and I think maxwell+ has a variant of
On Fri, Jan 25, 2019 at 10:58 AM Ilia Mirkin wrote:
>
> IMAD_S24 isn't src0 * src1 + src2 though. I think this could be called
> imad24, which I suspect exits on many GPUs (nv50-era NVIDIA definitely
> had this, and I think maxwell+ has a variant of this implemented by
> XMAD):
>
> (src0 * src1)
IMAD_S24 isn't src0 * src1 + src2 though. I think this could be called
imad24, which I suspect exits on many GPUs (nv50-era NVIDIA definitely
had this, and I think maxwell+ has a variant of this implemented by
XMAD):
(src0 * src1) & 0xff + src2
Cheers,
-ilia
On Fri, Jan 25, 2019 at 10:49
ir3 compiler has an integer multiply-add instruction (IMAD_S24)
that is used for different offset calculations in the backend.
Since we intend to move some of these calculations to NIR, we need
a new ALU op that can represent it.
---
src/compiler/nir/nir_opcodes.py | 1 +
1 file changed, 1
There are a bunch of instructions emitted on ir3_compiler_nir related to
offset computations for IO opcodes (ssbo, image, etc). This small series
explores the possibility of moving these instructions to NIR, where we
have higher chances of optimizing them.
The series introduces a new, freedreno
This effectively removes all offset calculations in
ir3_compiler_nir::get_image_offset().
No regressions observed on affected tests from Khronos CTS and piglit
suites, compared to master.
Collecting useful stats on helps/hurts caused by this pass is WIP. Very
few shaders in shader-db data-base
This pass moves to NIR some offset calculations that are currently
implemented on the backend compiler, to allow NIR to possibly
optimize them.
For now, only coordinate byte-offset calculations for imageStore
and image atomic operations are implemented.
---
src/freedreno/Makefile.sources
This is an internal intrinsic intended to be injected by a
(freedreno-specific) 'lower_sampler_io' pass that will be introduced
later in this series; and consumed by ir3_compiler_nir.
The intrinsic will load in SSA values for various constants
for images (image_dims), namely the format's
On Thu, 24 Jan 2019 at 16:58, Daniel Vetter wrote:
>
> If a non-legacy driver calls these it's valid to assume there is
> interrupt support. The flag is really only needed for legacy drivers.
... legacy drivers which issue the IRQ via the DRM_IOCTL_CONTROL legacy IOCTL.
At a later stage, we
Hi Daniel.
On Thu, Jan 24, 2019 at 05:58:06PM +0100, Daniel Vetter wrote:
> If a non-legacy driver calls these it's valid to assume there is
> interrupt support. The flag is really only needed for legacy drivers.
>
> Also remove all the flag usage from non-legacy drivers.
>
> Signed-off-by:
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