From: Sharat Masetty
The last level system cache can be partitioned to 32 different
slices of which GPU has two slices preallocated. One slice is
used for caching GPU buffers and the other slice is used for
caching the GPU SMMU pagetables. This talks to the core system
cache driver to acquire the
Add a quirk IO_PGTABLE_QUIRK_SYS_CACHE to override the
attributes set in TCR for the page table walker when
using system cache.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/io-pgtable-arm.c | 7 ++-
include/linux/io-pgtable.h | 4
2 files changed, 10 insertions(+), 1 deletion
There are few places in arm-smmu-impl where there are
extra blank lines, remove them and while at it fix the
checkpatch warning for space required before the open
parenthesis.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 5 +
1 file changed, 1 insertion(
Use table and of_match_node() to match qcom implementation
instead of multiple of_device_compatible() calls for each
QCOM SMMU implementation.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff
From: Sharat Masetty
The register read-modify-write construct is generic enough
that it can be used by other subsystems as needed, create
a more generic rmw() function and have the gpu_rmw() use
this new function.
Signed-off-by: Sharat Masetty
Reviewed-by: Jordan Crouse
Signed-off-by: Sai Prak
Some hardware variants contain a system cache or the last level
cache(llc). This cache is typically a large block which is shared
by multiple clients on the SOC. GPU uses the system cache to cache
both the GPU data buffers(like textures) as well the SMMU pagetables.
This helps with improved render
Add iommu domain attribute for using system cache aka last level
cache by client drivers like GPU to set right attributes for caching
the hardware pagetables into the system cache.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm/arm-smmu/arm-smmu.c | 17 +
drivers/iommu/a
The clk_pre/clk_post values in shared_timings are used instead, and these
are unused.
Signed-off-by: Jonathan Marek
Tested-by: Dmitry Baryshkov (SM8250)
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
b/driver
Note I haven't tested SM8150 recently, but DSI is almost identical to SM8250.
v2:
- added workaround for 5GHz max_rate overflowing in 32-bit builds
(based on robclark's suggestion)
- Updated Kconfig option to mention SM8250 and not just SM8150
Jonathan Marek (3):
drm/msm/dsi: remove unused
This allows DSI driver to work with sm8150 and sm8250. The sdm845 config
is re-used as the config is the same.
Signed-off-by: Jonathan Marek
Tested-by: Dmitry Baryshkov (SM8250)
---
drivers/gpu/drm/msm/dsi/dsi_cfg.c | 5 -
drivers/gpu/drm/msm/dsi/dsi_cfg.h | 2 ++
2 files changed, 6 inserti
This adds support for the 7nm ("V4") DSI PHY/PLL for sm8150 and sm8250.
Implementation is based on 10nm driver, but updated based on the downstream
7nm driver.
Signed-off-by: Jonathan Marek
Tested-by: Dmitry Baryshkov (SM8250)
---
.../devicetree/bindings/display/msm/dsi.txt | 6 +-
drivers
On 2020-09-11 15:28, Sai Prakash Ranjan wrote:
There are few places in arm-smmu-impl where there are
extra blank lines, remove them
FWIW those were deliberate - sometimes I like a bit of subtle space to
visually delineate distinct groups of definitions. I suppose it won't be
to everyone's tas
On Fri, Sep 11, 2020 at 05:03:06PM +0100, Robin Murphy wrote:
> BTW am I supposed to have received 3 copies of everything? Because I did...
Yeah, this seems to be happening for all of Sai's emails :/
Will
___
Freedreno mailing list
Freedreno@lists.freed
The function iommu_domain_alloc returns NULL on platforms without IOMMU
such as msm8974. This resulted in PTR_ERR(-ENODEV) being assigned to
gpu->aspace so the correct code path wasn't taken.
Fixes: ccac7ce373c1 ("drm/msm: Refactor address space initialization")
Signed-off-by: Luca Weiss
---
dri
On 2020-09-11 21:33, Robin Murphy wrote:
On 2020-09-11 15:28, Sai Prakash Ranjan wrote:
There are few places in arm-smmu-impl where there are
extra blank lines, remove them
FWIW those were deliberate - sometimes I like a bit of subtle space to
visually delineate distinct groups of definitions.
On 2020-09-11 21:37, Will Deacon wrote:
On Fri, Sep 11, 2020 at 05:03:06PM +0100, Robin Murphy wrote:
BTW am I supposed to have received 3 copies of everything? Because I
did...
Yeah, this seems to be happening for all of Sai's emails :/
Sorry, I am not sure what went wrong as I only sent t
On 2020-09-11 17:21, Sai Prakash Ranjan wrote:
On 2020-09-11 21:37, Will Deacon wrote:
On Fri, Sep 11, 2020 at 05:03:06PM +0100, Robin Murphy wrote:
BTW am I supposed to have received 3 copies of everything? Because I
did...
Yeah, this seems to be happening for all of Sai's emails :/
Sorry
On 2020-09-11 22:04, Robin Murphy wrote:
On 2020-09-11 17:21, Sai Prakash Ranjan wrote:
On 2020-09-11 21:37, Will Deacon wrote:
On Fri, Sep 11, 2020 at 05:03:06PM +0100, Robin Murphy wrote:
BTW am I supposed to have received 3 copies of everything? Because I
did...
Yeah, this seems to be hap
add event thread to execute events serially from event queue. Also
timeout mode is supported which allow an event be deferred to be
executed at later time. Both link and phy compliant tests had been
done successfully.
Changes in v2:
-- Fix potential deadlock by removing redundant connect_mutex
--
On Fri, Sep 11, 2020 at 06:08:53PM +0200, Luca Weiss wrote:
> The function iommu_domain_alloc returns NULL on platforms without IOMMU
> such as msm8974. This resulted in PTR_ERR(-ENODEV) being assigned to
> gpu->aspace so the correct code path wasn't taken.
>
> Fixes: ccac7ce373c1 ("drm/msm: Refac
20 matches
Mail list logo
