Re: [Freedreno] [PATCH 3/4] drm/msm: fix -Woverride-init warning

Quoting Arnd Bergmann (2020-10-26 12:41:03) > From: Arnd Bergmann > > There is one harmless duplicate initialization that causes a warning > with 'make W=1': > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c:122:19: warning: initialized > field overwritten [-Woverride-init] > 122 |

Re: [Freedreno] [PATCH 3/4] drm/msm: fix -Woverride-init warning

On 2020-10-26 12:41, Arnd Bergmann wrote: From: Arnd Bergmann There is one harmless duplicate initialization that causes a warning with 'make W=1': drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c:122:19: warning: initialized field overwritten [-Woverride-init] 122 | .max_linewidth = 4096,

[Freedreno] [PATCH 3/4] drm/msm: fix -Woverride-init warning

From: Arnd Bergmann There is one harmless duplicate initialization that causes a warning with 'make W=1': drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c:122:19: warning: initialized field overwritten [-Woverride-init] 122 | .max_linewidth = 4096, | ^~~~

[Freedreno] [PATCH] drm/msm/a6xx: Add support for using system cache on MMU500 based targets

This is an extension to the series [1] to enable the System Cache (LLC) for Adreno a6xx targets. GPU targets with an MMU-500 attached have a slightly different process for enabling system cache. Use the compatible string on the IOMMU phandle to see if an MMU-500 is attached and modify the

Re: [Freedreno] [PATCHv6 4/6] drm/msm/a6xx: Add support for using system cache(LLC)

On Mon, Oct 26, 2020 at 05:24:03PM +0530, Sai Prakash Ranjan wrote: > From: Sharat Masetty > > The last level system cache can be partitioned to 32 different > slices of which GPU has two slices preallocated. One slice is > used for caching GPU buffers and the other slice is used for > caching

Re: [Freedreno] [PATCHv6 3/6] drm/msm: rearrange the gpu_rmw() function

On Mon, Oct 26, 2020 at 05:24:02PM +0530, Sai Prakash Ranjan wrote: > From: Sharat Masetty > > The register read-modify-write construct is generic enough > that it can be used by other subsystems as needed, create > a more generic rmw() function and have the gpu_rmw() use > this new function. >

Re: [Freedreno] [PATCH] drm/msm: Add missing stub definition

On Mon, Oct 26, 2020 at 5:48 AM Robin Murphy wrote: > > DRM_MSM fails to build with DRM_MSM_DP=n; add the missing stub. > > Signed-off-by: Robin Murphy Thanks.. Reviewed-by: Rob Clark and looks like, Fixes: 8ede2ecc3e5e ("drm/msm/dp: Add DP compliance tests on Snapdragon Chipsets") > --- >

Re: [Freedreno] [PATCH v2 3/3] dt-bindings: drm/msm/gpu: Add cooling device support

On Mon, Oct 19, 2020 at 06:44:28PM +0530, Akhil P Oommen wrote: > Add cooling device support to gpu. A cooling device is bound to a > thermal zone to allow thermal mitigation. > > Signed-off-by: Akhil P Oommen > --- > Documentation/devicetree/bindings/display/msm/gpu.txt | 7 +++ > 1 file

[Freedreno] [PATCH] drm/msm: Add missing stub definition

DRM_MSM fails to build with DRM_MSM_DP=n; add the missing stub. Signed-off-by: Robin Murphy --- drivers/gpu/drm/msm/msm_drv.h | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index b9dd8f8f4887..0b2686b060c7 100644 ---

[Freedreno] [PATCHv6 6/6] iommu: arm-smmu-impl: Add a space before open parenthesis

Fix the checkpatch warning for space required before the open parenthesis. Signed-off-by: Sai Prakash Ranjan --- drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c

[Freedreno] [PATCHv6 0/6] System Cache support for GPU and required SMMU support

Some hardware variants contain a system cache or the last level cache(llc). This cache is typically a large block which is shared by multiple clients on the SOC. GPU uses the system cache to cache both the GPU data buffers(like textures) as well the SMMU pagetables. This helps with improved render

[Freedreno] [PATCHv6 1/6] iommu/io-pgtable-arm: Add support to use system cache

Add a quirk IO_PGTABLE_QUIRK_SYS_CACHE to override the attributes set in TCR for the page table walker when using system cache. Signed-off-by: Sai Prakash Ranjan --- drivers/iommu/io-pgtable-arm.c | 7 ++- include/linux/io-pgtable.h | 4 2 files changed, 10 insertions(+), 1

[Freedreno] [PATCHv6 4/6] drm/msm/a6xx: Add support for using system cache(LLC)

From: Sharat Masetty The last level system cache can be partitioned to 32 different slices of which GPU has two slices preallocated. One slice is used for caching GPU buffers and the other slice is used for caching the GPU SMMU pagetables. This talks to the core system cache driver to acquire

[Freedreno] [PATCHv6 2/6] iommu/arm-smmu: Add domain attribute for system cache

Add iommu domain attribute for using system cache aka last level cache by client drivers like GPU to set right attributes for caching the hardware pagetables into the system cache. Signed-off-by: Sai Prakash Ranjan --- drivers/iommu/arm/arm-smmu/arm-smmu.c | 17 +

[Freedreno] [PATCHv6 3/6] drm/msm: rearrange the gpu_rmw() function

From: Sharat Masetty The register read-modify-write construct is generic enough that it can be used by other subsystems as needed, create a more generic rmw() function and have the gpu_rmw() use this new function. Signed-off-by: Sharat Masetty Reviewed-by: Jordan Crouse Signed-off-by: Sai

[Freedreno] [PATCHv6 5/6] iommu: arm-smmu-impl: Use table to list QCOM implementations

Use table and of_match_node() to match qcom implementation instead of multiple of_device_compatible() calls for each QCOM SMMU implementation. Signed-off-by: Sai Prakash Ranjan --- drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 9 + drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 21

Re: [Freedreno] [PATCH v4 23/23] drm/msm: Don't implicit-sync if only a single ring

On Fri, Oct 23, 2020 at 08:49:14PM -0700, Rob Clark wrote: > On Fri, Oct 23, 2020 at 11:20 AM Lucas Stach wrote: > > > > On Fr, 2020-10-23 at 09:51 -0700, Rob Clark wrote: > > > From: Rob Clark > > > > > > If there is only a single ring (no-preemption), everything is FIFO order > > > and there