On 2020-10-27 03:23, Dmitry Baryshkov wrote:
c33b7c0389e1 ("drm/msm/dpu: add support for clk and bw scaling for
display") has added support for handling bandwidth voting in kms path
in
addition to old mdss path. However this broke all other platforms since
_dpu_core_perf_crtc_update_bus() will
On 2020-10-27 21:10, Robin Murphy wrote:
On 2020-10-26 18:54, Jordan Crouse wrote:
This is an extension to the series [1] to enable the System Cache
(LLC) for
Adreno a6xx targets.
GPU targets with an MMU-500 attached have a slightly different process
for
enabling system cache. Use the
On 2020-10-27 20:09, Jordan Crouse wrote:
On Tue, Oct 27, 2020 at 12:38:02PM +0530, Sai Prakash Ranjan wrote:
On 2020-10-27 00:24, Jordan Crouse wrote:
>This is an extension to the series [1] to enable the System Cache (LLC)
>for
>Adreno a6xx targets.
>
>GPU targets with an MMU-500 attached
On 2020-10-26 18:54, Jordan Crouse wrote:
This is an extension to the series [1] to enable the System Cache (LLC) for
Adreno a6xx targets.
GPU targets with an MMU-500 attached have a slightly different process for
enabling system cache. Use the compatible string on the IOMMU phandle
to see if
On Tue, Oct 27, 2020 at 12:38:02PM +0530, Sai Prakash Ranjan wrote:
> On 2020-10-27 00:24, Jordan Crouse wrote:
> >This is an extension to the series [1] to enable the System Cache (LLC)
> >for
> >Adreno a6xx targets.
> >
> >GPU targets with an MMU-500 attached have a slightly different process
Hi Abhinav,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-exynos/exynos-drm-next]
[also build test WARNING on drm-intel/for-linux-next
tegra-drm/drm/tegra/for-next drm-tip/drm-tip linus/master v5.10-rc1
next-20201027]
[cannot apply to drm/drm-next
On 25-10-20, 10:39, Rob Clark wrote:
> Nope, I suspect any creation of debugfs files will be problematic.
Yeah, so it only fixed part of the problem.
> (btw, _add_opp_dev_unlocked() looks like it should be called
> _add_opp_dev_locked()?)
>
> It does look like 'struct opp_table' is already
c33b7c0389e1 ("drm/msm/dpu: add support for clk and bw scaling for
display") has added support for handling bandwidth voting in kms path in
addition to old mdss path. However this broke all other platforms since
_dpu_core_perf_crtc_update_bus() will now error out instead of properly
calculating
Hello,
On 04/08/2020 18:40, Rob Clark wrote:
On Thu, Jul 16, 2020 at 4:36 AM Kalyan Thota wrote:
This change adds support to scale src clk and bandwidth as
per composition requirements.
Interconnect registration for bw has been moved to mdp
device node from mdss to facilitate the scaling.
Hi Abhinav,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-exynos/exynos-drm-next]
[also build test WARNING on drm-intel/for-linux-next
tegra-drm/drm/tegra/for-next drm-tip/drm-tip linus/master v5.10-rc1
next-20201026]
[cannot apply to drm/drm-next]
[If
On 2020-10-27 00:24, Jordan Crouse wrote:
This is an extension to the series [1] to enable the System Cache (LLC)
for
Adreno a6xx targets.
GPU targets with an MMU-500 attached have a slightly different process
for
enabling system cache. Use the compatible string on the IOMMU phandle
to see
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