Re: [Freedreno] [RESEND 00/53] Rid GPU from W=1 warnings

On Thu, 11 Mar 2021, Lee Jones wrote: > On Thu, 11 Mar 2021, Daniel Vetter wrote: > > > On Mon, Mar 08, 2021 at 09:19:32AM +, Lee Jones wrote: > > > On Fri, 05 Mar 2021, Roland Scheidegger wrote: > > > > > > > The vmwgfx ones look all good to me, so for > > > > 23-53: Reviewed-by: Roland Sch

[Freedreno] [PATCH v1 00/26] drm/msm/dsi: refactor MSM DSI PHY/PLL drivers

Restructure MSM DSI PHY drivers. What started as an attempt to grok the overcomplicated PHY drivers, has lead up to the idea of merging PHY and PLL code, reducing abstractions, code duplication, dropping dead code, etc. The patches were mainly tested on RB5 (sm8250, 7nm) and DB410c (apq8016, 28nm-

[Freedreno] [PATCH v1 02/26] clk: divider: add devm_clk_hw_register_divider

Add devm_clk_hw_register_divider() - devres version of clk_hw_register_divider(). Signed-off-by: Dmitry Baryshkov --- include/linux/clk-provider.h | 17 + 1 file changed, 17 insertions(+) diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 3eb15e0262f5

[Freedreno] [PATCH v1 01/26] clk: mux: provide devm_clk_hw_register_mux()

Add devm_clk_hw_register_mux() - devres-managed version of clk_hw_register_mux(). Signed-off-by: Dmitry Baryshkov --- drivers/clk/clk-mux.c| 35 +++ include/linux/clk-provider.h | 13 + 2 files changed, 48 insertions(+) diff --git a/drivers/cl

[Freedreno] [PATCH v1 04/26] drm/msm/dsi: drop multiple pll enable_seq support

The only PLL using multiple enable sequences is the 28nm PLL, which just does the single step in the loop. Push that support back into the PLL code. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c| 3 +- drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c| 23 +

[Freedreno] [PATCH v1 05/26] drm/msm/dsi: move all PLL callbacks into PHY config struct

Move all PLL-related callbacks into struct msm_dsi_phy_cfg. This limits the amount of data in the struct msm_dsi_pll. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/dsi.h | 6 -- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 14 +-- drivers/gpu/drm/msm/dsi/phy/dsi

[Freedreno] [PATCH v1 06/26] drm/msm/dsi: move min/max PLL rate to phy config

Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 3 +++ drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 6 -- drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 6 -- drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 10 ++ drivers/gpu/drm/

[Freedreno] [PATCH v1 09/26] arm64: dts: qcom: sm8250: assign DSI clock source parents

Assign DSI clock source parents to DSI PHY clocks. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 6 ++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 947e1accae3a..b6ed94497e8a 1006

[Freedreno] [PATCH v1 07/26] drm/msm/dsi: remove msm_dsi_pll_set_usecase

msm_dsi_pll_set_usecase() function is not used outside of individual DSI PHY drivers, so drop it in favour of calling the the respective set_usecase functions directly. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/dsi.h | 7 --- drivers/gpu/drm/msm/dsi/phy/dsi_phy

[Freedreno] [PATCH v1 11/26] drm/msm/dsi: push provided clocks handling into a generic code

All MSM DSI PHYs provide two clocks: byte and pixel ones. Register/unregister provided clocks from the generic place, removing boilerplate code from all MSM DSI PHY drivers. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 23 ++ drivers/gpu/drm/msm/dsi

[Freedreno] [PATCH v1 14/26] drm/msm/dsi: replace PHY's init callback with configurable data

DSI PHY init callback would either map dsi_phy_regulator or dsi_phy_lane depending on the PHY type. Replace those callbacks with configuration options governing mapping those regions. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 42 --- driv

[Freedreno] [PATCH v1 16/26] drm/msm/dsi: limit vco_delay to 28nm PHY

Only 28nm PHY requires sleeping during the VCO rate setting procedure. Rewrite sleeping for 28nm and drop vco_delay from the rest of PHYs. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 3 --- drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 4 drivers/gpu/dr

[Freedreno] [PATCH v1 17/26] drm/msi/dsi: inline msm_dsi_pll_helper_clk_prepare/unprepare

10nm and 7nm already do not use these helpers, as they handle setting slave DSI clocks after enabling VCO. Modify the rest of PHY drivers to remove unnecessary indirection and drop enable_seq/disable_seq PLL callbacks. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/phy/dsi_phy.h

[Freedreno] [PATCH v1 12/26] drm/msm/dsi: use devm_clk_*register to registe DSI PHY clocks

Use devres-enabled version of clock registration functions. This lets us remove dsi_pll destroy callbacks completely. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/dsi.h | 4 - drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 - drivers/gpu/drm/msm/dsi/phy/dsi_ph

[Freedreno] [PATCH v1 08/26] drm/msm/dsi: stop setting clock parents manually

There is no reason to set clock parents manually, use device tree to assign DSI/display clock parents to DSI PHY clocks. Dropping this manual setup allows us to drop repeating code and to move registration of hw clock providers to generic place. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/dr

[Freedreno] [PATCH v1 13/26] drm/msm/dsi: use devm_of_clk_add_hw_provider

Use devm_of_clk_add_hw_provider() to register provided clocks. This allows dropping the remove function alltogether. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 22 +- 1 file changed, 1 insertion(+), 21 deletions(-) diff --git a/drivers/gpu/dr

[Freedreno] [PATCH v1 10/26] arm64: dts: qcom: sdm845: assign DSI clock source parents

Assign DSI clock source parents to DSI PHY clocks. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 6 ++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 454f794af547..2166549382c1 1006

[Freedreno] [PATCH v1 19/26] drm/msm/dsi: drop msm_dsi_pll abstracton

Drop the struct msm_dsi_pll abstraction, by including vco's clk_hw directly into struct msm_dsi_phy. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/Kconfig | 8 -- drivers/gpu/drm/msm/Makefile | 2 - drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 36

[Freedreno] [PATCH v1 18/26] drm/msm/dsi: make save_state/restore_state callbacks accept msm_dsi_phy

Make save_state/restore callbacks accept struct msm_dsi_phy rather than struct msm_dsi_pll. This moves them to struct msm_dsi_phy_ops, allowing us to drop struct msm_dsi_pll_ops. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 12 +++ drivers/gpu/drm/msm/d

[Freedreno] [PATCH v1 15/26] drm/msm/dsi: make save/restore_state phy-level functions

Morph msm_dsi_pll_save/restore_state() into msm_dsi_phy_save/restore_state(), thus removing last bits of knowledge about msm_dsi_pll from dsi_manager. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/dsi.h | 18 ++- drivers/gpu/drm/msm/dsi/dsi_manager.c | 6

[Freedreno] [PATCH v1 23/26] drm/msm/dsi: remove temp data from global pll structure

The 7nm, 10nm and 14nm drivers would store interim data used during VCO/PLL rate setting in the global dsi_pll_Nnm structure. Move this data structures to the onstack storage. While we are at it, drop unused/static 'config' data, unused config fields, etc. Signed-off-by: Dmitry Baryshkov --- dri

[Freedreno] [PATCH v1 22/26] drm/msm/dsi: remove duplicate fields from dsi_pll_Nnm instances

Drop duplicate fields pdev and id from dsi_pll_Nnm instances. Reuse those fields from the provided msm_dsi_phy. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c| 72 +-- drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c| 54 +++--- drivers/g

[Freedreno] [PATCH v1 26/26] drm/msm/dsi: stop passing src_pll_id to the phy_enable call

Phy driver already knows the source PLL id basing on the set usecase and the current PLL id. Stop passing it to the phy_enable call. As a reminder, dsi manager will always use DSI 0 as a clock master in a slave mode, so PLL 0 is always a clocksource for DSI 0 and it is always a clocksource for DSI

[Freedreno] [PATCH v1 21/26] drm/msm/dsi: move ioremaps to dsi_phy_driver_probe

All PHY drivers would map dsi_pll area. Some PHY drivers would also map dsi_phy area again (a leftover from old PHY/PLL separation). Move all ioremaps to the common dsi_phy driver code and drop individual ioremapped areas from PHY drivers. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/

[Freedreno] [PATCH v1 20/26] drm/msm/dsi: drop PLL accessor functions

Replace PLL accessor functions (pll_read/pll_write*) with the DSI PHY accessors, reducing duplication. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 24 +-- drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c| 124 drivers/gpu/drm/msm/dsi/phy/ds

[Freedreno] [PATCH v1 24/26] drm/msm/dsi: drop global msm_dsi_phy_type enumaration

With the current upstream driver the msm_dsi_phy_type enum does not make much sense: all DSI PHYs are probed using the dt bindings, the phy type is not passed between drivers. Use quirks in phy individual PHY drivers to differentiate minor harware differences and drop the enum. Signed-off-by: Dmit

[Freedreno] [PATCH v1 25/26] drm/msm/dsi: inline msm_dsi_phy_set_src_pll

The src_truthtable config is not used for some of phys, which use other means of configuring the master/slave usecases. Inline this function with the goal of removing src_pll_id argument in the next commit. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 17

Re: [Freedreno] [PATCH] gpu/drm/msm: fix shutdown hook in case GPU components failed to bind

On Mon, Mar 1, 2021 at 1:41 PM Dmitry Baryshkov wrote: > > if GPU components have failed to bind, shutdown callback would fail with > the following backtrace. Add safeguard check to stop that oops from > happening and allow the board to reboot. > > [ 66.617046] Unable to handle kernel NULL point

[Freedreno] [PATCH] drm/msm: Ratelimit invalid-fence message

From: Rob Clark We have seen a couple cases where low memory situations cause something bad to happen, followed by a flood of these messages obscuring the root cause. Lets ratelimit the dmesg spam so that next time it happens we don't loose the kernel traces leading up to this. Signed-off-by: R

Re: [Freedreno] [PATCH] drm/msm: Ratelimit invalid-fence message

Hi, On Wed, Mar 17, 2021 at 9:40 AM Rob Clark wrote: > > From: Rob Clark > > We have seen a couple cases where low memory situations cause something > bad to happen, followed by a flood of these messages obscuring the root > cause. Lets ratelimit the dmesg spam so that next time it happens we >

Re: [Freedreno] [RESEND 00/53] Rid GPU from W=1 warnings

On Wed, Mar 17, 2021 at 9:17 AM Lee Jones wrote: > > On Thu, 11 Mar 2021, Lee Jones wrote: > > > On Thu, 11 Mar 2021, Daniel Vetter wrote: > > > > > On Mon, Mar 08, 2021 at 09:19:32AM +, Lee Jones wrote: > > > > On Fri, 05 Mar 2021, Roland Scheidegger wrote: > > > > > > > > > The vmwgfx ones l

[Freedreno] [PATCH] drm/msm/dp: Fixed couple of typos

s/modueles/modules/ two different places Signed-off-by: Bhaskar Chowdhury --- drivers/gpu/drm/msm/dp/dp_power.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_power.h b/drivers/gpu/drm/msm/dp/dp_power.h index 7d0327bbc0d5..e3f959ffae12 1006