On Mon 10 May 07:16 CDT 2021, sbill...@codeaurora.org wrote:
> On 2021-05-06 20:32, Rob Clark wrote:
> > On Wed, May 5, 2021 at 11:47 PM wrote:
> > >
> > > On 2021-05-05 15:31, Dmitry Baryshkov wrote:
> > > > Hi,
> > > >
> > > > On Wed, 5 May 2021 at 11:17, Sankeerth Billakanti
> > > > wrote:
The eDP controller found in SC8180x is at large compatible with the
current implementation, but has its register blocks at slightly
different offsets.
Add the compatible and the new register layout.
Signed-off-by: Bjorn Andersson
---
drivers/gpu/drm/msm/dp/dp_display.c | 1 +
Some bootloaders set the widebus enable bit in the INTF_CONFIG register,
but configuration of widebus isn't yet supported ensure that the
register has a known value, with widebus disabled.
Fixes: c943b4948b58 ("drm/msm/dp: add displayPort driver support")
Signed-off-by: Bjorn Andersson
---
Not all platforms has DP_P0 at offset 0x1000 from the beginning of the
DP block. So move the offsets into dss_io_data, to make it possible in
the next patch to specify alternative offsets and sizes of these
segments.
Signed-off-by: Bjorn Andersson
---
drivers/gpu/drm/msm/dp/dp_catalog.c | 57
In the search for causes to timing issues seen during implementation of
eDP support for SC8180x a fair amount of time was spent concluding why
the calculated mvid/nvid values where wrong.
The overall conclusion is that the ratio of MVID/NVID describes, and
should match, the ratio between the
The first patch in the series is somewhat unrelated to the support, but
simplifies reasoning and debugging of timing related issues.
The second patch introduces support for dealing with different register block
layouts, which is used in the forth patch to describe the hardware blocks found
in the
From: Rob Clark
Add SC8180x to the hardware catalog, for initial support for the
platform. Due to limitations in the DP driver only one of the four DP
interfaces is left enabled.
The SC8180x platform supports the newly added DPU_INTF_WIDEBUS flag and
the Windows-on-Snapdragon bootloader leaves
It's typical for the bootloader to configure CTL_0 for the boot splash
or EFIFB, but for non-DSI use cases the DPU driver tend to pick another
CTL and the system might end up with two configured data paths producing
data on the same INTF - with resulting graphical artifacts.
Naturally the end
Some hardware supports clocking 2 pixels per pixel clock pulse, known as
"widebus". The configuration needs to match between the DPU and the
interface controller, and the timing parameters must be adjusted.
As a first step towards supporting this, start by adding a INTF mask
flag to signal the
Signed-off-by: Bjorn Andersson
---
This is a hack and as discussed on IRC this should be replaced by some sane
mechanism for dealing with the old and new IRQ layout. Including it in the
series for completeness.
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 14 ++
1 file
These patches adds MDSS and DPU support for the Qualcomm SC8180x platform.
The platform supports running 2 pixels per pixel clock cycle and the bootloader
enables this, so the first patch adds enough support to the DPU driver to
disable this again.
The second patch shoots down the data path
Quoting Zhen Lei (2021-05-09 23:38:05)
> The error code returned by platform_get_irq() is stored in 'irq', it's
> forgotten to be copied to 'ret' before being returned. As a result, the
> value 0 of 'ret' is returned incorrectly.
>
> After the above fix is completed, initializing the local
Sorry, what patch are you referring to?
Alex
On Mon, May 10, 2021 at 4:04 AM wrote:
>
> I have tested this on my end and it resolves the 120hz problem.
>
> Tested-By: Ryan Houdek
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On 10/05/2021 04:16, Zhen Lei wrote:
v1 --> v2:
According to Anton Ivanov's review comments, detele the unnecessary local
variable initialization "ret = 0".
Zhen Lei (1):
drm/msm/dpu: Fix error return code in dpu_mdss_init()
drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 8 +---
1 file
On 2021-05-06 20:32, Rob Clark wrote:
On Wed, May 5, 2021 at 11:47 PM wrote:
On 2021-05-05 15:31, Dmitry Baryshkov wrote:
> Hi,
>
> On Wed, 5 May 2021 at 11:17, Sankeerth Billakanti
> wrote:
>>
>> These patches add support for the next generation eDP driver on
>> SnapDragon
>> with dpu
v1 --> v2:
According to Stephen Boyd's review comments, detele the unnecessary local
variable initialization "ret = 0".
Zhen Lei (1):
drm/msm/dpu: Fix error return code in dpu_mdss_init()
drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
The error code returned by platform_get_irq() is stored in 'irq', it's
forgotten to be copied to 'ret' before being returned. As a result, the
value 0 of 'ret' is returned incorrectly.
After the above fix is completed, initializing the local variable 'ret'
to 0 is no longer needed, remove it.
In
On 2021/5/10 14:01, Anton Ivanov wrote:
> On 10/05/2021 04:16, Zhen Lei wrote:
>> v1 --> v2:
>> According to Anton Ivanov's review comments, detele the unnecessary local
>> variable initialization "ret = 0".
>>
>>
>> Zhen Lei (1):
>> drm/msm/dpu: Fix error return code in dpu_mdss_init()
>>
>>
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