On Tue, May 25, 2021 at 11:46 PM Vinod Koul wrote:
>
> Hello Jeff,
>
> On 21-05-21, 08:09, Jeffrey Hugo wrote:
> > On Fri, May 21, 2021 at 6:50 AM Vinod Koul wrote:
> > >
> > > Display Stream Compression (DSC) compresses the display stream in host
> > > which
> > > is later decoded by panel. Thi
DP mainlink can be either enabled or disabled at the time of suspend
happen. Therefore DP phy teared down at suspend should base on mainlink
status at that instance.
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/dp/dp_ctrl.c| 5 -
drivers/gpu/drm/msm/dp/dp_ctrl.h| 2 +-
drivers
Quoting Kuogee Hsieh (2021-05-26 11:08:23)
> DP mainlink can be either enabled or disabled at the time of suspend
> happen. Therefore DP phy teared down at suspend should base on mainlink
> status at that instance.
Please add some more details here. The system crashes if you plug in the
HDMI cable
Aux channel is used to perform management function and should be
running in parallel with main link. Therefore should only power
down main link and keep aux channel running when power down phy.
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/dp/dp_ctrl.c| 4
drivers/phy/qualcomm/ph
On 2021-05-26 15:30, Stephen Boyd wrote:
Quoting Kuogee Hsieh (2021-05-26 11:08:23)
DP mainlink can be either enabled or disabled at the time of suspend
happen. Therefore DP phy teared down at suspend should base on
mainlink
status at that instance.
Please add some more details here. The sys
2021년 5월 21일 (금) 오후 1:16, Austin Kim 님이 작성:
>
> After the call to to_dpu_encoder_phys_cmd() is made,
> 'cmd_enc' is not used. Where to_dpu_encoder_phys_cmd() is simply replaced with
> container_of(x, struct dpu_encoder_phys_cmd, base) by compiler.
>
> So it had better remove W=1 kernel build warnin
General note, please Cc dri-devel on freedreno driver patches.
Quoting Kuogee Hsieh (2021-05-26 16:49:49)
> Aux channel is used to perform management function and should be
> running in parallel with main link. Therefore should only power
> down main link and keep aux channel running when power do
Crtc perf update from frame event work can result in
wrong bandwidth and clock update from dpu if the work
is scheduled after the swap state has happened.
Avoid such issues by moving perf update to complete
commit once the frame is accepted by the hardware.
Fixes: a29c8c024165 ("drm/msm/disp/dpu1
