On Wed 07 Jul 11:01 PDT 2021, Rob Clark wrote:
> From: Rob Clark
>
> It turns out that when the display is enabled by the bootloader, we can
> get some transient iommu faults from the display. Which doesn't go over
> too well when we install a fault handler that is gpu specific. To avoid
> thi
Many of the DSI flags have names opposite to their actual effects,
e.g. MIPI_DSI_MODE_EOT_PACKET means that EoT packets will actually
be disabled. Fix this by including _NO_ in the flag names, e.g.
MIPI_DSI_MODE_NO_EOT_PACKET.
Signed-off-by: Nicolas Boichat
Reviewed-by: Linus Walleij
Reviewed-by
Thank you Stephen for reviewing.
On 2021-07-26 14:31, Stephen Boyd wrote:
Quoting maitreye (2021-07-26 10:36:26)
@@ -509,6 +515,7 @@ static int dp_display_usbpd_attention_cb(struct
device *dev)
DRM_ERROR("invalid dev\n");
return -EINVAL;
}
+ DRM_DE
From: Maitreyee Rao
Add trace points across the MSM DP driver to help debug
interop issues.
Changes in v2:
- Got rid of redundant log messages.
- Added %#x instead of 0x%x wherever required.
- Got rid of __func__ calls in debug messages.
- Added newline wherever missing.
Changes in v3:
- G
Quoting Akhil P Oommen (2021-07-24 10:29:00)
> Add the necessary dt nodes for gpu support in sc7280.
>
> Signed-off-by: Akhil P Oommen
> ---
> This patch has dependency on the GPUCC bindings patch here:
> https://patchwork.kernel.org/project/linux-arm-msm/patch/1619519590-3019-4-git-send-email-t..
Quoting Bjorn Andersson (2021-07-24 21:24:32)
> Functions in the DisplayPort code that relates to individual instances
> (encoders) are passed both the struct msm_dp and the struct drm_encoder. But
> in a situation where multiple DP instances would exist this means that
> the caller need to resolve
Quoting Bjorn Andersson (2021-07-24 21:24:36)
> The sc8180x has 2 DP and 1 eDP controllers, add support for these to the
> DP driver.
>
> Link:
> https://lore.kernel.org/linux-arm-msm/20210511042043.592802-5-bjorn.anders...@linaro.org/
> Signed-off-by: Bjorn Andersson
> ---
> drivers/gpu/drm/msm
Quoting Bjorn Andersson (2021-07-24 21:24:35)
> The Qualcomm SC8180x has 2 DP controllers and 1 eDP controller, add
> compatibles for these to the msm/dp binding.
>
> Signed-off-by: Bjorn Andersson
> ---
Reviewed-by: Stephen Boyd
___
Freedreno mailing
Quoting Bjorn Andersson (2021-07-24 21:24:33)
> diff --git a/drivers/gpu/drm/msm/dp/dp_display.c
> b/drivers/gpu/drm/msm/dp/dp_display.c
> index 59ffd6c8f41f..92b7646a1bb7 100644
> --- a/drivers/gpu/drm/msm/dp/dp_display.c
> +++ b/drivers/gpu/drm/msm/dp/dp_display.c
> @@ -238,8 +251,11 @@ static i
eDP panels might need some power sequencing and backlight management,
so make it possible to associate a drm_panel with a DP instance and
prepare and enable the panel accordingly.
Signed-off-by: Bjorn Andersson
---
This solves my immediate problem on my 8cx laptops, of indirectly controlling
the
Quoting Bjorn Andersson (2021-07-24 21:24:31)
> As the Qualcomm DisplayPort driver only supports a single instance of
> the driver the commonly used struct dp_display is kept in a global
> variable. As we introduce additional instances this obviously doesn't
> work.
>
> Replace this with a combinat
Quoting Kuogee Hsieh (2021-07-23 09:55:39)
> There is a scenario that dp cable is unplugged from DUT during system
> suspended will cause audio option state does not match real connection
> state. Fix this problem by Signaling audio plugged change with realtime
> connection status at dp_pm_resume(
Quoting maitreye (2021-07-26 10:36:26)
> @@ -509,6 +515,7 @@ static int dp_display_usbpd_attention_cb(struct device
> *dev)
> DRM_ERROR("invalid dev\n");
> return -EINVAL;
> }
> + DRM_DEBUG_DP("sink_request: %d\n", sink_request);
This one is bad. sink
Quoting Kuogee Hsieh (2021-07-23 09:55:39)
> There is a scenario that dp cable is unplugged from DUT during system
> suspended will cause audio option state does not match real connection
> state. Fix this problem by Signaling audio plugged change with realtime
> connection status at dp_pm_resume(
Quoting maitreye (2021-07-26 10:36:26)
> From: Maitreyee Rao
>
> Add trace points across the MSM DP driver to help debug
> interop issues.
>
> Changes in v2:
> - Got rid of redundant log messages.
> - Added %#x instead of 0x%x wherever required.
> - Got rid of __func__ calls in debug messages.
On Wed, Jul 7, 2021 at 10:57 AM Rob Clark wrote:
>
> From: Rob Clark
>
> It turns out that when the display is enabled by the bootloader, we can
> get some transient iommu faults from the display. Which doesn't go over
> too well when we install a fault handler that is gpu specific. To avoid
>
From: Maitreyee Rao
Add trace points across the MSM DP driver to help debug
interop issues.
Changes in v2:
- Got rid of redundant log messages.
- Added %#x instead of 0x%x wherever required.
- Got rid of __func__ calls in debug messages.
- Added newline wherever missing.
Changes in v3:
- G
From: Rob Clark
Mark all the bos in the submit as active, before pinning, to prevent
evicting a buffer in the same submit to make room for a buffer earlier
in the table.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_gem.c| 2 --
drivers/gpu/drm/msm/msm_gem_submit.c | 28 +++
From: Rob Clark
The drm/scheduler provides additional prioritization on top of that
provided by however many number of ringbuffers (each with their own
priority level) is supported on a given generation. Expose the
additional levels of priority to userspace and map the userspace
priority back to
From: Rob Clark
It is sufficient to serialize on the submit queue now.
Signed-off-by: Rob Clark
Acked-by: Christian König
---
drivers/gpu/drm/msm/msm_gem_submit.c | 12 +---
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c
b/drivers/g
From: Rob Clark
For existing adrenos, there is one or more ringbuffer, depending on
whether preemption is supported. When preemption is supported, each
ringbuffer has it's own priority. A submitqueue (which maps to a
gl context or vk queue in userspace) is mapped to a specific ring-
buffer at c
From: Rob Clark
In the next patch, we start having more than a single potential failure
reason.
Signed-off-by: Rob Clark
Acked-by: Christian König
---
drivers/gpu/drm/msm/msm_gem_submit.c | 21 +
1 file changed, 9 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/dr
From: Rob Clark
Previously the (non-fd) fence returned from submit ioctl was a raw
seqno, which is scoped to the ring. But from UABI standpoint, the
ioctls related to seqno fences all specify a submitqueue. We can
take advantage of that to replace the seqno fences with a cyclic idr
handle.
Thi
From: Rob Clark
Move all the locked/active/pinned state handling to msm_gem_submit.c.
In particular, for drm/scheduler, we'll need to do all this before
pushing the submit job to the scheduler. But while we're at it we can
get rid of the dupicate pin and refcnt.
Signed-off-by: Rob Clark
Acked-
From: Rob Clark
No need for this to be split in two parts.
Signed-off-by: Rob Clark
Acked-by: Christian König
---
drivers/gpu/drm/msm/msm_gem_submit.c | 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c
b/drivers/gpu/drm/msm/msm
From: Rob Clark
No idea why we were still using this. It certainly hasn't been needed
for some time. So drop the pointless twin codepaths.
Signed-off-by: Rob Clark
Acked-by: Christian König
---
drivers/gpu/drm/msm/adreno/a5xx_debugfs.c | 4 +-
drivers/gpu/drm/msm/adreno/a5xx_gpu.c
From: Rob Clark
If we don't have a gpu, there is no need to create a submitqueue, which
lets us simplify the error handling and submitqueue creation.
Signed-off-by: Rob Clark
Acked-by: Christian König
---
drivers/gpu/drm/msm/msm_submitqueue.c | 22 +++---
1 file changed, 11 in
From: Rob Clark
Fix a couple incorrect or misspelt comments, and add submitqueue doc
comment.
Signed-off-by: Rob Clark
Acked-by: Christian König
---
drivers/gpu/drm/msm/msm_gem.h | 3 +--
drivers/gpu/drm/msm/msm_gem_submit.c | 1 +
drivers/gpu/drm/msm/msm_gpu.h | 15 +++
From: Rob Clark
Conversion to gpu_scheduler, and bonus removal of
drm_gem_object_put_locked()
v2: Fix priority mixup (msm UAPI has lower numeric priority value as
higher priority, inverse of drm/scheduler) and add some comments
in the UAPI header to clarify.
Now that we move active
From: Rob Clark
This adds a few things to try and make frequency scaling better match
the workload:
1) Longer polling interval to avoid whip-lashing between too-high and
too-low frequencies in certain workloads, like mobile games which
throttle themselves to 30fps.
Previously our polli
From: Rob Clark
In the next patch, it grows a bit more, so lets not duplicate the logic
in multiple places.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_gpu_devfreq.c | 21 ++---
1 file changed, 10 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_gpu
From: Rob Clark
Before we start adding more cleverness, split it into it's own file.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/Makefile | 1 +
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 4 +-
drivers/gpu/drm/msm/msm_gpu.c | 116 +-
drivers/gpu/drm/m
From: Rob Clark
This is the outcome of trying to fix some bad gpu freq behavior seen in
some use-cases, in particular mobile games that throttle themselves to
30fps. With the existing tuning, we'd end up spending most of the time
that we should be running fast at a low freq, and most of the idle
From: Rob Clark
Let dma_fence::signaled, etc, read directly from the address that the hw
is writing with updated completed fence seqno, so we can potentially
notice that the fence is signaled sooner.
Plus add some docs.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_fence.c | 11 ++
From: Rob Clark
Nothing we do to in update_fences() can't be done in an atomic context,
so move this into the GPU's irq context to reduce latency (and call
dma_fence_signal() so we aren't relying on dma_fence_is_signaled() which
would defeat the purpose).
Signed-off-by: Rob Clark
---
drivers/g
From: Rob Clark
A couple tweaks to reduce fence signal latency.
Rob Clark (2):
drm/msm: Let fences read directly from memptrs
drm/msm: Signal fences sooner
drivers/gpu/drm/msm/msm_fence.c | 11 +--
drivers/gpu/drm/msm/msm_fence.h | 41 +++---
drivers/gpu/d
Hi Nicolas,
On Mon, Jul 26, 2021 at 08:38:18AM +0800, Nicolas Boichat wrote:
> On Sun, Jul 25, 2021 at 9:31 PM Sam Ravnborg wrote:
> >
> > On Tue, Jun 29, 2021 at 07:47:21AM +0800, Nicolas Boichat wrote:
> > > Many of the DSI flags have names opposite to their actual effects,
> > > e.g. MIPI_DSI_
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