Both voltage and pre-emphasis swing level are set during link training
negotiation between host and sink. There are totally four tables added.
A voltage swing table for both hbr and hbr1, a voltage table for both
hbr2 and hbr3, a pre-emphasis table for both hbr and hbr1 and a pre-emphasis
table for
Quoting Kuogee Hsieh (2021-09-09 12:49:58)
> Existing display port phy reg property is derived from usb phy which
> map display port phy pcs to wrong address which cause aux init
> with wrong address and prevent both dpcd read and write from working.
> Fix this problem by assigning correct pcs addr
On Thu, Sep 9, 2021 at 12:50 PM Akhil P Oommen wrote:
>
> On 9/9/2021 9:42 PM, Amit Pundir wrote:
> > On Thu, 9 Sept 2021 at 17:47, Amit Pundir wrote:
> >>
> >> On Wed, 8 Sept 2021 at 07:50, Bjorn Andersson
> >> wrote:
> >>>
> >>> On Mon 09 Aug 10:26 PDT 2021, Akhil P Oommen wrote:
> >>>
>
Existing display port phy reg property is derived from usb phy which
map display port phy pcs to wrong address which cause aux init
with wrong address and prevent both dpcd read and write from working.
Fix this problem by assigning correct pcs address to display port
phy reg property.
Changes in V
On 9/9/2021 9:42 PM, Amit Pundir wrote:
On Thu, 9 Sept 2021 at 17:47, Amit Pundir wrote:
On Wed, 8 Sept 2021 at 07:50, Bjorn Andersson
wrote:
On Mon 09 Aug 10:26 PDT 2021, Akhil P Oommen wrote:
On 8/9/2021 9:48 PM, Caleb Connolly wrote:
On 09/08/2021 17:12, Rob Clark wrote:
On Mon, Au
Il 09/09/21 15:46, Dmitry Baryshkov ha scritto:
On 08/09/2021 17:22, Jeffrey Hugo wrote:
On Wed, Sep 8, 2021 at 2:26 AM Dmitry Baryshkov
wrote:
Hi,
On Tue, 7 Sept 2021 at 22:13, Jeffrey Hugo wrote:
On Wed, Sep 1, 2021 at 12:11 PM AngeloGioacchino Del Regno
wrote:
Bringup functionality
On Thu, Sep 9, 2021 at 9:42 AM Simon Ser wrote:
>
> On Thursday, September 9th, 2021 at 18:31, Rob Clark
> wrote:
>
> > Yes, I think it would.. and "dma-buf/sync_file: Add SET_DEADLINE
> > ioctl" adds such an ioctl.. just for the benefit of igt tests at this
> > point, but the thought was it wou
On Thursday, September 9th, 2021 at 18:31, Rob Clark
wrote:
> Yes, I think it would.. and "dma-buf/sync_file: Add SET_DEADLINE
> ioctl" adds such an ioctl.. just for the benefit of igt tests at this
> point, but the thought was it would be also used by compositors that
> are doing such frame sch
On Thu, Sep 9, 2021 at 9:16 AM Simon Ser wrote:
>
> Out of curiosity, would it be reasonable to allow user-space (more
> precisely, the compositor) to set the deadline via an IOCTL without
> actually performing an atomic commit with the FB?
>
> Some compositors might want to wait themselves for FB
Out of curiosity, would it be reasonable to allow user-space (more
precisely, the compositor) to set the deadline via an IOCTL without
actually performing an atomic commit with the FB?
Some compositors might want to wait themselves for FB fence completions
to ensure a client doesn't block the whol
On Thu, 9 Sept 2021 at 17:47, Amit Pundir wrote:
>
> On Wed, 8 Sept 2021 at 07:50, Bjorn Andersson
> wrote:
> >
> > On Mon 09 Aug 10:26 PDT 2021, Akhil P Oommen wrote:
> >
> > > On 8/9/2021 9:48 PM, Caleb Connolly wrote:
> > > >
> > > >
> > > > On 09/08/2021 17:12, Rob Clark wrote:
> > > > > On M
On Wed, Sep 8, 2021 at 10:27 PM Petri Latvala wrote:
>
> On Wed, Sep 08, 2021 at 11:02:42AM -0700, Rob Clark wrote:
> > On Mon, Aug 30, 2021 at 9:18 AM Rob Clark wrote:
> > >
> > > From: Rob Clark
> > >
> > > Add an initial set of tests for the gpu SUBMIT ioctl. There is
> > > plenty more we ca
On 08/09/2021 17:22, Jeffrey Hugo wrote:
On Wed, Sep 8, 2021 at 2:26 AM Dmitry Baryshkov
wrote:
Hi,
On Tue, 7 Sept 2021 at 22:13, Jeffrey Hugo wrote:
On Wed, Sep 1, 2021 at 12:11 PM AngeloGioacchino Del Regno
wrote:
Bringup functionality for MSM8998 in the DPU, driver which is mostly
th
On Wed, 8 Sept 2021 at 07:50, Bjorn Andersson
wrote:
>
> On Mon 09 Aug 10:26 PDT 2021, Akhil P Oommen wrote:
>
> > On 8/9/2021 9:48 PM, Caleb Connolly wrote:
> > >
> > >
> > > On 09/08/2021 17:12, Rob Clark wrote:
> > > > On Mon, Aug 9, 2021 at 7:52 AM Akhil P Oommen
> > > > wrote:
> [..]
> > > >
From: David Heidelberg
[ Upstream commit 56bd931ae506730c9ab1e4cc4bfefa43fc2d18fa ]
msm_atomic is doing vblank get/put's already,
currently there no need to duplicate the effort in MDP4
Fix warning:
...
WARNING: CPU: 3 PID: 79 at drivers/gpu/drm/drm_vblank.c:1194
drm_vblank_put+0x1cc/0x1d4
...
From: Kuogee Hsieh
[ Upstream commit 7948fe12d47a946fb8025a0534c900e3dd4b5839 ]
Response with correct edid checksum saved at connector after corrupted edid
checksum read. This fixes Link Layer CTS cases 4.2.2.3, 4.2.2.6.
Signed-off-by: Kuogee Hsieh
Reviewed-by: Stephen Boyd
Link:
https://lor
From: Konrad Dybcio
[ Upstream commit 462f7017a6918d152870bfb8852f3c70fd74b296 ]
VDDA is not present and the specified load value is wrong. Fix it.
Signed-off-by: Konrad Dybcio
Link:
https://lore.kernel.org/r/20210728222057.52641-1-konrad.dyb...@somainline.org
Reviewed-by: Dmitry Baryshkov
S
From: David Heidelberg
[ Upstream commit 56bd931ae506730c9ab1e4cc4bfefa43fc2d18fa ]
msm_atomic is doing vblank get/put's already,
currently there no need to duplicate the effort in MDP4
Fix warning:
...
WARNING: CPU: 3 PID: 79 at drivers/gpu/drm/drm_vblank.c:1194
drm_vblank_put+0x1cc/0x1d4
...
From: Kuogee Hsieh
[ Upstream commit 2e0adc765d884cc080baa501e250bfad97035b09 ]
Initialize both pre-emphasis and voltage swing level to 0 before
start link training and do not end link training until video is
ready to reduce the period between end of link training and video
start to meet Link La
From: Kuogee Hsieh
[ Upstream commit 7948fe12d47a946fb8025a0534c900e3dd4b5839 ]
Response with correct edid checksum saved at connector after corrupted edid
checksum read. This fixes Link Layer CTS cases 4.2.2.3, 4.2.2.6.
Signed-off-by: Kuogee Hsieh
Reviewed-by: Stephen Boyd
Link:
https://lor
From: Kuogee Hsieh
[ Upstream commit 4b85d405cfe938ae7ad61656484ae88dee289e3b ]
Reduce link rate and re start link training if link training 1
failed due to loss of clock recovery done to fix Link Layer
CTS case 4.3.1.7. Also only update voltage and pre-emphasis
swing level after link training
From: Konrad Dybcio
[ Upstream commit 462f7017a6918d152870bfb8852f3c70fd74b296 ]
VDDA is not present and the specified load value is wrong. Fix it.
Signed-off-by: Konrad Dybcio
Link:
https://lore.kernel.org/r/20210728222057.52641-1-konrad.dyb...@somainline.org
Reviewed-by: Dmitry Baryshkov
S
From: David Heidelberg
[ Upstream commit 56bd931ae506730c9ab1e4cc4bfefa43fc2d18fa ]
msm_atomic is doing vblank get/put's already,
currently there no need to duplicate the effort in MDP4
Fix warning:
...
WARNING: CPU: 3 PID: 79 at drivers/gpu/drm/drm_vblank.c:1194
drm_vblank_put+0x1cc/0x1d4
...
From: Kuogee Hsieh
[ Upstream commit 2e0adc765d884cc080baa501e250bfad97035b09 ]
Initialize both pre-emphasis and voltage swing level to 0 before
start link training and do not end link training until video is
ready to reduce the period between end of link training and video
start to meet Link La
From: Kuogee Hsieh
[ Upstream commit 7948fe12d47a946fb8025a0534c900e3dd4b5839 ]
Response with correct edid checksum saved at connector after corrupted edid
checksum read. This fixes Link Layer CTS cases 4.2.2.3, 4.2.2.6.
Signed-off-by: Kuogee Hsieh
Reviewed-by: Stephen Boyd
Link:
https://lor
From: Kuogee Hsieh
[ Upstream commit 0b324564ff74fa0556002be8fbbace556b9b2ad0 ]
Aux hardware calibration sequence requires resetting the aux controller
in order for the new setting to take effect. However resetting the AUX
controller will also clear HPD interrupt status which may accidentally
ca
From: Kuogee Hsieh
[ Upstream commit 4b85d405cfe938ae7ad61656484ae88dee289e3b ]
Reduce link rate and re start link training if link training 1
failed due to loss of clock recovery done to fix Link Layer
CTS case 4.3.1.7. Also only update voltage and pre-emphasis
swing level after link training
From: Konrad Dybcio
[ Upstream commit 462f7017a6918d152870bfb8852f3c70fd74b296 ]
VDDA is not present and the specified load value is wrong. Fix it.
Signed-off-by: Konrad Dybcio
Link:
https://lore.kernel.org/r/20210728222057.52641-1-konrad.dyb...@somainline.org
Reviewed-by: Dmitry Baryshkov
S
From: David Heidelberg
[ Upstream commit 56bd931ae506730c9ab1e4cc4bfefa43fc2d18fa ]
msm_atomic is doing vblank get/put's already,
currently there no need to duplicate the effort in MDP4
Fix warning:
...
WARNING: CPU: 3 PID: 79 at drivers/gpu/drm/drm_vblank.c:1194
drm_vblank_put+0x1cc/0x1d4
...
From: Akhil P Oommen
[ Upstream commit a6f24383f6c0a8d64d1f6afa10733ae4e8f236e0 ]
Add the missing scache_cntl0 register programing which is required for
a660 gpu.
Signed-off-by: Akhil P Oommen
Link:
https://lore.kernel.org/r/20210730011945.v4.1.I110b87677ef16d97397fb7c81c07a16e1f5d211e@change
30 matches
Mail list logo
