Hi Dmitry
On 6/15/2022 10:55 PM, Dmitry Baryshkov wrote:
On 14/06/2022 22:32, Abhinav Kumar wrote:
intf and wb resources are not dependent on the rm global
state so need not be allocated during dpu_encoder_virt_atomic_mode_set().
Move the allocation of intf and wb resources to
On 14/06/2022 22:32, Abhinav Kumar wrote:
intf and wb resources are not dependent on the rm global
state so need not be allocated during dpu_encoder_virt_atomic_mode_set().
Move the allocation of intf and wb resources to dpu_encoder_setup_display()
so that we can utilize the hw caps even during
Quoting Dmitry Baryshkov (2022-05-04 17:16:04)
> diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
> index a37a3bbc04d9..98ae0036ab57 100644
> --- a/drivers/gpu/drm/msm/msm_drv.c
> +++ b/drivers/gpu/drm/msm/msm_drv.c
> @@ -262,6 +263,46 @@ static int msm_drm_uninit(struct
Quoting Kuogee Hsieh (2022-06-15 08:53:57)
> Display resolution change is implemented through drm modeset. Older
> modeset (resolution) has to be disabled first before newer modeset
> (resolution) can be enabled. Display disable will turn off both
> pixel clock and main link clock so that main
On 6/15/2022 11:42 AM, Dmitry Baryshkov wrote:
On 15/06/2022 20:55, Abhinav Kumar wrote:
On 5/4/2022 5:16 PM, Dmitry Baryshkov wrote:
Follow the lead of MDP5 driver and check both DPU and MDSS devices for
the IOMMU specifiers.
Historically DPU devices had IOMMU specified in the MDSS
After [1] was merged to IGT, we use either the first supported
mode in the list OR the preferred mode to determine the primary
plane to use for the sub-test due to the IGT API [2].
Since writeback does not set any preferred mode, this was
selecting 4k as that was the first entry in the list.
We
Hi Dmitry,
On Wed, 15 Jun 2022 17:19:42 +0300 Dmitry Baryshkov
wrote:
>
> I would appreciate if you could add
>
> https://gitlab.freedesktop.org/lumag/msm.git msm-next-lumag
>
> to the linux-next tree.
>
> This tree is a part of drm/msm maintenance structure. As a co-maintainer I
> collect
On Thu, 16 Jun 2022 at 00:22, Abhinav Kumar wrote:
>
> intf and wb resources are not dependent on the rm global
> state so need not be allocated during dpu_encoder_virt_atomic_mode_set().
>
> Move the allocation of intf and wb resources to dpu_encoder_setup_display()
> so that we can utilize the
Remove the hard-coded limit for writeback and lets start using
the one from catalog instead.
Fixes: d7d0e73f7de3 ("introduce the dpu_encoder_phys_* for writeback")
Signed-off-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 6 ++
1
Writeback block for sm8250 was using the default maxlinewidth
of 2048. But this is not right as it supports upto 4096.
This should have no effect on most resolutions as we are
still limiting upto maxlinewidth of SSPP for adding the modes.
Fix the maxlinewidth for writeback block on sm8250.
intf and wb resources are not dependent on the rm global
state so need not be allocated during dpu_encoder_virt_atomic_mode_set().
Move the allocation of intf and wb resources to dpu_encoder_setup_display()
so that we can utilize the hw caps even during atomic_check() phase.
Since
On 09/06/2022 05:23, Dmitry Baryshkov wrote:
> Convert Qualcomm HDMI binding into HDMI TX and PHY yaml bindings.
>
> Changes to schema:
> HDMI:
> - fixed reg-names numbering to match 0..3 instead 0,1,3,4
> - dropped qcom,tx-ddc-* from example, they were not documented
> - make phy-names
On 15/06/2022 20:55, Abhinav Kumar wrote:
On 5/4/2022 5:16 PM, Dmitry Baryshkov wrote:
Follow the lead of MDP5 driver and check both DPU and MDSS devices for
the IOMMU specifiers.
Historically DPU devices had IOMMU specified in the MDSS device tree
node, but as some of MDP5 devices are being
On 6/15/2022 11:34 AM, Dmitry Baryshkov wrote:
On 15/06/2022 20:11, Abhinav Kumar wrote:
On 6/15/2022 10:04 AM, Dmitry Baryshkov wrote:
On 15/06/2022 19:40, Abhinav Kumar wrote:
On 6/15/2022 5:36 AM, Dmitry Baryshkov wrote:
On 14/06/2022 22:32, Abhinav Kumar wrote:
intf and wb
On 15/06/2022 20:11, Abhinav Kumar wrote:
On 6/15/2022 10:04 AM, Dmitry Baryshkov wrote:
On 15/06/2022 19:40, Abhinav Kumar wrote:
On 6/15/2022 5:36 AM, Dmitry Baryshkov wrote:
On 14/06/2022 22:32, Abhinav Kumar wrote:
intf and wb resources are not dependent on the rm global
state so
On 5/4/2022 5:16 PM, Dmitry Baryshkov wrote:
Even if some IOMMU has registered itself on the platform "bus", that
doesn't necessarily mean it provides translation for the device we
care about. Replace iommu_present() with a more appropriate check.
On Qualcomm platforms the IOMMU can be
On 5/4/2022 5:16 PM, Dmitry Baryshkov wrote:
Move iommu_domain_alloc() in front of adress space/IOMMU initialization.
This allows us to drop final bits of struct mdp5_cfg_platform which
remained from the pre-DT days.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
On 6/15/22 10:01 AM, Rob Clark wrote:
From: Rob Clark
Prior to the last commit, this could result in setting the GPU
written fence value back to an older value, if we had missed
updating completed_fence prior to suspend. This was mostly
harmless as the GPU would eventually overwrite it
On 6/15/22 10:01 AM, Rob Clark wrote:
From: Rob Clark
I noticed while looking at some traces, that we could miss calls to
msm_update_fence(), as the irq could have raced with retire_submits()
which could have already popped the last submit on a ring out of the
queue of in-flight submits.
On 6/15/2022 9:17 AM, Dmitry Baryshkov wrote:
On 15/06/2022 19:11, Jessica Zhang wrote:
On 6/15/2022 2:35 AM, Dmitry Baryshkov wrote:
On Wed, 15 Jun 2022 at 00:13, Jessica Zhang
wrote:
Move layer mixer-specific section of dpu_crtc_get_crc() into a separate
helper method. This way, we can
On 5/4/2022 5:16 PM, Dmitry Baryshkov wrote:
Follow the lead of MDP5 driver and check both DPU and MDSS devices for
the IOMMU specifiers.
Historically DPU devices had IOMMU specified in the MDSS device tree
node, but as some of MDP5 devices are being converted to the supported
by the DPU
On 6/15/2022 10:04 AM, Dmitry Baryshkov wrote:
On 15/06/2022 19:40, Abhinav Kumar wrote:
On 6/15/2022 5:36 AM, Dmitry Baryshkov wrote:
On 14/06/2022 22:32, Abhinav Kumar wrote:
intf and wb resources are not dependent on the rm global
state so need not be allocated during
On 15/06/2022 19:40, Abhinav Kumar wrote:
On 6/15/2022 5:36 AM, Dmitry Baryshkov wrote:
On 14/06/2022 22:32, Abhinav Kumar wrote:
intf and wb resources are not dependent on the rm global
state so need not be allocated during
dpu_encoder_virt_atomic_mode_set().
Move the allocation of intf
On 6/15/2022 5:36 AM, Dmitry Baryshkov wrote:
On 14/06/2022 22:32, Abhinav Kumar wrote:
intf and wb resources are not dependent on the rm global
state so need not be allocated during dpu_encoder_virt_atomic_mode_set().
Move the allocation of intf and wb resources to
From: Rob Clark
In debugging fence rollover, I noticed that GPU state capture and
devcore dumps were showing me negative fence numbers. Let's fix that
and some related signed vs unsigned confusion.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 10 +-
1 file
From: Rob Clark
And while we are at it, let's start the fence counter close to the
rollover point so that if issues slip in, they are more obvious.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_fence.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git
On 15/06/2022 19:11, Jessica Zhang wrote:
On 6/15/2022 2:35 AM, Dmitry Baryshkov wrote:
On Wed, 15 Jun 2022 at 00:13, Jessica Zhang
wrote:
Move layer mixer-specific section of dpu_crtc_get_crc() into a separate
helper method. This way, we can make it easier to get CRCs from other HW
blocks
On 6/15/2022 2:44 AM, Dmitry Baryshkov wrote:
On Wed, 15 Jun 2022 at 00:13, Jessica Zhang wrote:
Add support for writing CRC values for the interface block to
the debugfs by calling the necessary MISR setup/collect methods.
Changes since V1:
- Set values_cnt to only include phys with
On 6/15/2022 2:35 AM, Dmitry Baryshkov wrote:
On Wed, 15 Jun 2022 at 00:13, Jessica Zhang wrote:
Move layer mixer-specific section of dpu_crtc_get_crc() into a separate
helper method. This way, we can make it easier to get CRCs from other HW
blocks by adding other get_crc helper methods.
Display resolution change is implemented through drm modeset. Older
modeset (resolution) has to be disabled first before newer modeset
(resolution) can be enabled. Display disable will turn off both
pixel clock and main link clock so that main link have to be
re-trained during display enable to
From: Rob Clark
Prior to the last commit, this could result in setting the GPU
written fence value back to an older value, if we had missed
updating completed_fence prior to suspend. This was mostly
harmless as the GPU would eventually overwrite it again with
the correct value. But we should
From: Rob Clark
I noticed while looking at some traces, that we could miss calls to
msm_update_fence(), as the irq could have raced with retire_submits()
which could have already popped the last submit on a ring out of the
queue of in-flight submits. But walking the list of submits in the
irq
On Sat, Jun 11, 2022 at 11:16 AM Steev Klimaszewski wrote:
>
> Hi Rob,
>
> On 6/10/22 12:20 PM, Rob Clark wrote:
> > From: Rob Clark
> >
> > Keep the warn, but drop the early return. If we do manage to hit this
> > sort of issue, skipping the cleanup just makes things worse (dangling
> >
Hi Stephen,
I would appreciate if you could add
https://gitlab.freedesktop.org/lumag/msm.git msm-next-lumag
to the linux-next tree.
This tree is a part of drm/msm maintenance structure. As a co-maintainer
I collect and test display patches, while Rob concenctrates on GPU part
of the driver.
Add MDP_CLK ("core") clock to the mdss device to allow MDSS driver to
access HW_REV/etc registers.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi
Move is_mdp5 check to a more logical place, to the msm_mdss_init(),
rather than getting it in the mdss_probe() and passing it then as an
argument.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_mdss.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
Rather than checking whether the platform is an mdp5 or dpu platform,
check if the MDP_CLK is provided or not before trying to access HW_REV
(and skip reading the registers if the clock is not provided by the DT).
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_mdss.c | 22
Enable (optional) core (MDP_CLK) clock that allows accessing HW_REV
registers during the platform init.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_mdss.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c
Replace magic register writes in msm_mdss_enable() with version that
contains less magic and more variable names that can be traced back to
the dpu_hw_catalog or the downstream dtsi files.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_mdss.c | 80
Am 15.06.22 um 14:45 schrieb Dmitry Baryshkov:
On 09/06/2022 20:42, Rob Clark wrote:
From: Rob Clark
The DEFINE_DRM_GEM_FOPS() helper is a bit limiting if a driver wants to
provide additional file ops, like show_fdinfo().
v2: Split out DRM_GEM_FOPS instead of making DEFINE_DRM_GEM_FOPS
Remove loops over hw_vbif. Instead always VBIF's idx as an index in the
array. This fixes an error in dpu_kms_hw_init(), where we fill
dpu_kms->hw_vbif[i], but check for an error pointer at
dpu_kms->hw_vbif[vbif_idx].
Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support")
Signed-off-by: Dmitry
Using IS_ERR_OR_NULL() together with PTR_ERR() is a typical mistake. If
the value is NULL, then the function will return 0 instead of a proper
return code. Moreover dpu_hw_vbif_init() function can not return NULL.
So, replace corresponding IS_ERR_OR_NULL() call with IS_ERR().
Reviewed-by: Abhinav
We do not expect to have other VBIFs. Drop VBIF_n indices and always use
VBIF_RT and VBIF_NRT.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 4 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 6 ++--
On 11/04/2022 23:47, Sean Paul wrote:
From: Sean Paul
Rebased set from November. Fixed a nit from Stephen in the msm patch and
moved hdcp registers into the trogdor dtsi file to avoid differences
with sc7180-based windows devices. The set is 4 patches lighter since
some of the changes were
On 09/06/2022 18:42, Rob Clark wrote:
From: Rob Clark
Similar to AMD commit
874442541133 ("drm/amdgpu: Add show_fdinfo() interface"), using the
infrastructure added in previous patches, we add basic client info
and GPU engine utilisation for msm.
Example output:
# cat /proc/`pgrep
On 26/04/2022 16:21, Wan Jiabing wrote:
Fix following coccicheck warning:
drivers/gpu/drm/msm/msm_gpu_devfreq.c:72:1-7: WARNING: do_div() does a 64-by-32
division, please consider using div64_ul instead.
Use div64_ul instead of do_div to avoid a possible truncation.
Signed-off-by: Wan Jiabing
On 09/06/2022 20:42, Rob Clark wrote:
From: Rob Clark
The DEFINE_DRM_GEM_FOPS() helper is a bit limiting if a driver wants to
provide additional file ops, like show_fdinfo().
v2: Split out DRM_GEM_FOPS instead of making DEFINE_DRM_GEM_FOPS
varardic
v3: nits
Signed-off-by: Rob Clark
On 09/06/2022 20:42, Rob Clark wrote:
From: Rob Clark
Similar to AMD commit
874442541133 ("drm/amdgpu: Add show_fdinfo() interface"), using the
infrastructure added in previous patches, we add basic client info
and GPU engine utilisation for msm.
Example output:
# cat /proc/`pgrep
On 14/06/2022 22:32, Abhinav Kumar wrote:
intf and wb resources are not dependent on the rm global
state so need not be allocated during dpu_encoder_virt_atomic_mode_set().
Move the allocation of intf and wb resources to dpu_encoder_setup_display()
so that we can utilize the hw caps even during
On 14/06/2022 22:32, Abhinav Kumar wrote:
Remove the hard-coded limit for writeback and lets start using
the one from catalog instead.
Fixes: d7d0e73f7de3 ("introduce the dpu_encoder_phys_* for writeback")
Signed-off-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
---
On 14/06/2022 22:32, Abhinav Kumar wrote:
Writeback block for sm8250 was using the default maxlinewidth
of 2048. But this is not right as it supports upto 4096.
This should have no effect on most resolutions as we are
still limiting upto maxlinewidth of SSPP for adding the modes.
Fix the
On 14/06/2022 22:32, Abhinav Kumar wrote:
intf and wb resources are not dependent on the rm global
state so need not be allocated during dpu_encoder_virt_atomic_mode_set().
Move the allocation of intf and wb resources to dpu_encoder_setup_display()
so that we can utilize the hw caps even during
On 11/06/2022 01:02, Luca Weiss wrote:
From: Vladimir Lypak
There is currently two function for performing reset: dsi_sw_reset and
dsi_sw_reset_restore. Only difference betwean those is that latter one
assumes that DSI controller is enabled. In contrary former one assumes
that controller is
On 03/06/2022 23:09, Kuogee Hsieh wrote:
Use quic id instead of codeaurora id in maintainers list
for display devicetree bindings.
Signed-off-by: Kuogee Hsieh
Reviewed-by: Dmitry Baryshkov
We can pick it through the msm/ tree, if no one objects.
---
On 03/06/2022 12:42, Vinod Polimera wrote:
During probe defer, drm device is not initialized and an external
trigger to shutdown is trying to clean up drm device leading to crash.
Add checks to avoid drm device cleanup in such cases.
BUG: unable to handle kernel NULL pointer dereference at
On 03/06/2022 12:42, Vinod Polimera wrote:
During probe defer, drm device is not initialized and an external
trigger to shutdown is trying to clean up drm device leading to crash.
Add checks to avoid drm device cleanup in such cases.
BUG: unable to handle kernel NULL pointer dereference at
On 01/05/2022 18:12, Dmitry Baryshkov wrote:
The commit 0f40ba48de3b ("drm/msm/dsi: Pass DSC params to drm_panel")
added a pointer to the DSC data to the struct drm_panel. However DSC
support is not limited to the DSI panels. MIPI DSI bridges can also
consume DSC command streams. Thus add struct
Make dp_connector_mode_valid() return precise MODE_CLOCK_HIGH rather
than generic MODE_BAD in case the mode clock is higher than
DP_MAX_PIXEL_CLK_KHZ (675 MHz).
Reviewed-by: Kuogee Hsieh
Reviewed-by: Stephen Boyd
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dp/dp_display.c | 2 +-
1
On 21/02/2022 17:51, Vinod Polimera wrote:
Use atomic variants for encoder callback functions such that
certain states like self-refresh can be accessed as part of
enable/disable sequence.
Signed-off-by: Kalyan Thota
Signed-off-by: Vinod Polimera
Changes in v2:
- As per review suggestion by
On Wed, 15 Jun 2022 at 02:01, Emma Anholt wrote:
>
> Required for turning on per-process page tables for the GPU.
>
> Signed-off-by: Emma Anholt
Reviewed-by: Dmitry Baryshkov
> ---
>
> drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git
On Wed, 15 Jun 2022 at 02:01, Emma Anholt wrote:
>
> This is an SMMU for the adreno gpu, and adding this compatible lets
> the driver use per-fd page tables, which are required for security
> between GPU clients.
>
> Signed-off-by: Emma Anholt
> ---
>
> Tested with a full deqp-vk run on RB5,
On Wed, 15 Jun 2022 at 00:13, Jessica Zhang wrote:
>
> Add support for writing CRC values for the interface block to
> the debugfs by calling the necessary MISR setup/collect methods.
>
> Changes since V1:
> - Set values_cnt to only include phys with backing hw_intf
> - Loop over all drm_encs
On Wed, 15 Jun 2022 at 00:13, Jessica Zhang wrote:
>
> Add support for setting MISR registers within the interface
>
> Changes since V1:
> - Replaced dpu_hw_intf collect_misr and setup_misr implementations with
> calls to dpu_hw_utils helper methods
>
> Signed-off-by: Jessica Zhang
On Wed, 15 Jun 2022 at 00:13, Jessica Zhang wrote:
>
> Move layer mixer-specific section of dpu_crtc_get_crc() into a separate
> helper method. This way, we can make it easier to get CRCs from other HW
> blocks by adding other get_crc helper methods.
>
> Changes since V1:
> - Moved common
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