of_icc_get() alloc resources for path1, we should release it when not
need anymore. Early return when IS_ERR_OR_NULL(path0) may leak path1.
Defer getting path1 to fix this.
Fixes: b9364eed9232 ("drm/msm/dpu: Move min BW request and full BW disable back
to mdss")
Signed-off-by: Miaoqian Lin
---
From: Vinod Koul
Add the HDMI display nodes and link it to DSI.
Signed-off-by: Vinod Koul
Reviewed-by: Krzysztof Kozlowski
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 37 +
1 file changed, 37 insertions(+)
Enable MDSS/DPU/DSI0 on SM8450-HDK device.
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts
Add devices tree nodes describing display hardware on SM8450:
- Display Clock Controller
- MDSS
- MDP
- two DSI controllers and DSI PHYs
This does not provide support for DP controllers present on SM8450.
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
Add another power saving state used on SM8450. Unfortunately adding it
in proper place causes renumbering of all the opp states in sm8450.dtsi
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sm8450.dtsi | 20
Add device tree nodes for MDSS, DPU and DSI devices on Qualcomm SM8450
platform. Enable these devices and add the HDMI bridge configuration on
SM8450 HDK.
Changes since v3:
- Renamed mdss node to display-subsystem@ (Krzysztof)
- Dropped empty line from the patch4 (Krzysztof)
- Renamed HDMI
From: Vinod Koul
Add the LT9611uxc DSI-HDMI bridge and supplies
Signed-off-by: Vinod Koul
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 58 +
1 file changed, 58 insertions(+)
diff --git
Add support for the MDSS block on SM8450 platform.
Tested-by: Vinod Koul
Reviewed-by: Vinod Koul
Reviewed-by: Konrad Dybcio
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_mdss.c | 5 +
1 file changed, 5 insertions(+)
diff --git
There is a separate header containing some of MDP TOP register
definitions, dpu_hwio.h. Move missing register definitions from
dpu_hw_top.c to the mentioned header.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 25 --
On sm8450 a register block was removed from MDP TOP. Accessing it during
snapshotting results in NoC errors / immediate reboot. Skip accessing
these registers during snapshot.
Tested-by: Vinod Koul
Reviewed-by: Vinod Koul
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
Add support for DSI 2.6.0 (block used on sm8450).
Tested-by: Vinod Koul
Reviewed-by: Vinod Koul
Reviewed-by: Konrad Dybcio
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dsi/dsi_cfg.c | 2 ++
drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 +
2 files changed, 3
Add DPU and MDSS schemas to describe MDSS and DPU blocks on the Qualcomm
SM8450 platform.
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Dmitry Baryshkov
---
.../bindings/display/msm/qcom,sm8450-dpu.yaml | 139 +++
.../display/msm/qcom,sm8450-mdss.yaml | 343 ++
2
Add definitions for the display hardware used on Qualcomm SM8450
platform.
Tested-by: Vinod Koul
Reviewed-by: Vinod Koul
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 224 ++
In preparation to adding the sm8350 and sm8450 PHYs support, rearrange
register values calculations in dsi_7nm_phy_enable(). This change bears
no functional changes itself, it is merely a preparation for the next
patch.
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
Require only properties declared in given schema, which makes the code a
bit more readable and easy to follow.
Suggested-by: Krzysztof Kozlowski
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Dmitry Baryshkov
---
Documentation/devicetree/bindings/display/msm/mdss-common.yaml | 1 -
SM8350 and SM8450 use 5nm DSI PHYs, which share register definitions
with 7nm DSI PHYs. Rather than duplicating the driver, handle 5nm
variants inside the common 5+7nm driver.
Co-developed-by: Robert Foss
Tested-by: Vinod Koul
Reviewed-by: Vinod Koul
Reviewed-by: Konrad Dybcio
Signed-off-by:
Require only properties declared in given schema, which makes the code a
bit more readable and easy to follow.
Suggested-by: Krzysztof Kozlowski
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Dmitry Baryshkov
---
.../devicetree/bindings/display/msm/dpu-common.yaml| 4
SM8350 and SM8450 platforms use the same driver and same bindings as the
existing 7nm DSI PHYs. Add corresponding compatibility strings.
Acked-by: Krzysztof Kozlowski
Signed-off-by: Dmitry Baryshkov
---
Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml | 2 ++
1 file changed, 2
This adds support for the MDSS/DPU/DSI on the Qualcomm SM8450 platform.
Change since v5:
- Added defines to be used for the MDP_PERIPH_TOP0 blackhole
Change since v4:
- Fixed commit messages for the first two patches (Krzysztof)
- Dropped clock-names requirement patch
- Removed clock-names from
On 25/11/2022 08:01, Abhinav Kumar wrote:
On 11/23/2022 1:04 PM, Dmitry Baryshkov wrote:
On sm8450 a register block was removed from MDP TOP. Accessing it during
snapshotting results in NoC errors / immediate reboot. Skip accessing
these registers during snapshot.
Tested-by: Vinod Koul
On 12/5/2022 2:10 PM, Dan Carpenter wrote:
> On Sun, Dec 04, 2022 at 04:11:41AM +0530, Akhil P Oommen wrote:
>> Fix the below kernel panic due to null pointer access:
>> [ 18.504431] Unable to handle kernel NULL pointer dereference at virtual
>> address 0048
>> [ 18.513464] Mem
On 12/2/2022 12:30 PM, Akhil P Oommen wrote:
> On 12/2/2022 4:27 AM, Bjorn Andersson wrote:
>> On Wed, Oct 05, 2022 at 02:36:58PM +0530, Akhil P Oommen wrote:
>> @Ulf, Akhil has a power-domain for a piece of hardware which may be
>> voted active by multiple different subsystems
From: Rob Clark
In cases where implicit sync is used, it is still useful (for things
like sub-allocation, etc) to allow userspace to opt-out of implicit
sync on per-BO basis.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_drv.c| 3 ++-
drivers/gpu/drm/msm/msm_gem_submit.c | 11
On Wed, 30 Nov 2022 21:09:38 +0100, Adam Skladowski wrote:
> This patch series adds bunch of new nodes
> also it fixes some small nitpicks in yamls and adds compatible.
>
> Changes since v1
>
> 1. Changed title for mdss yaml patch
> 2. Added missing dmas to spi0
> 3. Wired freq
On 12/6/2022 12:05 AM, Jiasheng Jiang wrote:
As kzalloc may fail and return NULL pointer,
it should be better to check cstate
in order to avoid the NULL pointer dereference
in __drm_atomic_helper_crtc_reset.
You have wrapped around your lines too short. Please try to utilize the
full word
Hi,
On Mon, Dec 5, 2022 at 11:55 PM Miaoqian Lin wrote:
>
> of_icc_get() alloc resources for path1, we should release it when not
> need anymore. Early return when IS_ERR_OR_NULL(path0) may leak path1.
> Add icc_put(path1) in the error path to fix this.
>
> Fixes: b9364eed9232 ("drm/msm/dpu:
On Mon, 05 Dec 2022 15:08:11 -0800, Kuogee Hsieh wrote:
> Add both data-lanes and link-frequencies property into endpoint
>
> Changes in v7:
> -- split yaml out of dtsi patch
> -- link-frequencies from link rate to symbol rate
> -- deprecation of old data-lanes property
>
> Changes in v8:
> --
As kzalloc may fail and return NULL pointer,
it should be better to check cstate
in order to avoid the NULL pointer dereference
in __drm_atomic_helper_crtc_reset.
Fixes: 1cff7440a86e ("drm/msm: Convert to using
__drm_atomic_helper_crtc_reset() for reset.")
Signed-off-by: Jiasheng Jiang
---
As kzalloc may fail and return NULL pointer,
it should be better to check pstates
in order to avoid the NULL pointer dereference.
Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support")
Signed-off-by: Jiasheng Jiang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 2 ++
1 file changed, 2
As kzalloc may fail and return NULL pointer,
it should be better to check pstates
in order to avoid the NULL pointer dereference
later.
Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support")
Signed-off-by: Jiasheng Jiang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 2 ++
1 file changed, 2
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