On 28.05.2023 19:07, Manivannan Sadhasivam wrote:
> On Tue, May 23, 2023 at 09:59:53AM +0200, Konrad Dybcio wrote:
>>
>>
>> On 23.05.2023 03:15, Bjorn Andersson wrote:
>>> From: Bjorn Andersson
>>>
>>> Add Adreno SMMU, GPU clock controller, GMU and GPU nodes for the
>>> SC8280XP.
>>>
>>> Signed
On 29.05.2023 04:42, Dmitry Baryshkov wrote:
> On Mon, 17 Apr 2023 at 18:30, Konrad Dybcio wrote:
>>
>> Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there's
>> another path that needs to be handled to ensure MDSS functions properly,
>> namely the "reg bus", a.k.a the CPU-MDSS int
On Mon, May 29, 2023 at 09:38:59AM +0200, Konrad Dybcio wrote:
>
>
> On 28.05.2023 19:07, Manivannan Sadhasivam wrote:
> > On Tue, May 23, 2023 at 09:59:53AM +0200, Konrad Dybcio wrote:
> >>
> >>
> >> On 23.05.2023 03:15, Bjorn Andersson wrote:
> >>> From: Bjorn Andersson
> >>>
> >>> Add Adreno
On 29/05/2023 10:42, Konrad Dybcio wrote:
On 29.05.2023 04:42, Dmitry Baryshkov wrote:
On Mon, 17 Apr 2023 at 18:30, Konrad Dybcio wrote:
Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there's
another path that needs to be handled to ensure MDSS functions properly,
namely the "
On 29.05.2023 10:47, Dmitry Baryshkov wrote:
> On 29/05/2023 10:42, Konrad Dybcio wrote:
>>
>>
>> On 29.05.2023 04:42, Dmitry Baryshkov wrote:
>>> On Mon, 17 Apr 2023 at 18:30, Konrad Dybcio
>>> wrote:
Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there's
another p
Add the required config for the v1.1 MDP5 found on MSM8226.
Signed-off-by: Luca Weiss
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 82
1 file changed, 82 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_
Add the compatible for the MDP5 found on MSM8226.
Signed-off-by: Luca Weiss
---
Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml
b/Documentation/devicetree/bindings/displ
MSM8226 uses a modified PLL lock sequence compared to MSM8974, which is
based on the function dsi_pll_enable_seq_m in the msm-3.10 kernel.
Worth noting that the msm-3.10 downstream kernel also will try other
sequences in case this one doesn't work, but during testing it has shown
that the _m seque
Add the nodes that describe the mdss so that display can work on
MSM8226.
Signed-off-by: Luca Weiss
---
arch/arm/boot/dts/qcom-msm8226.dtsi | 118
1 file changed, 118 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi
b/arch/arm/boot/dts/qcom-ms
This series adds the required configs for MDP5 and DSI blocks that are
needed for MDSS on MSM8226. Finally we can add the new nodes into the
dts.
Tested on apq8026-lg-lenok and msm8926-htc-memul.
Signed-off-by: Luca Weiss
---
Luca Weiss (7):
dt-bindings: msm: dsi-phy-28nm: Document msm8226
Add the compatible for the DSI found on MSM8226.
Signed-off-by: Luca Weiss
---
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
b/Documentation/dev
The MSM8226 SoC uses a slightly different 28nm dsi phy. Add a new
compatible for it.
Signed-off-by: Luca Weiss
---
Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml | 1 +
Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml| 1 +
2 files changed, 2 insertions(+)
diff
Add the config for the v1.0.2 DSI found on MSM8226. We can reuse
existing bits from other revisions that are identical for v1.0.2.
Signed-off-by: Luca Weiss
---
drivers/gpu/drm/msm/dsi/dsi_cfg.c | 2 ++
drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/drive
On 29/05/2023 12:08, Konrad Dybcio wrote:
On 29.05.2023 10:47, Dmitry Baryshkov wrote:
On 29/05/2023 10:42, Konrad Dybcio wrote:
On 29.05.2023 04:42, Dmitry Baryshkov wrote:
On Mon, 17 Apr 2023 at 18:30, Konrad Dybcio wrote:
Apart from the already handled data bus (MAS_MDP_Pn<->DDR), th
On 29.05.2023 11:44, Luca Weiss wrote:
> MSM8226 uses a modified PLL lock sequence compared to MSM8974, which is
> based on the function dsi_pll_enable_seq_m in the msm-3.10 kernel.
>
> Worth noting that the msm-3.10 downstream kernel also will try other
> sequences in case this one doesn't wor
On 29.05.2023 11:44, Luca Weiss wrote:
> Add the required config for the v1.1 MDP5 found on MSM8226.
>
> Signed-off-by: Luca Weiss
> ---
> drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 82
>
> 1 file changed, 82 insertions(+)
>
> diff --git a/drivers/gpu/drm/ms
On 29.05.2023 11:44, Luca Weiss wrote:
> Add the config for the v1.0.2 DSI found on MSM8226. We can reuse
> existing bits from other revisions that are identical for v1.0.2.
>
> Signed-off-by: Luca Weiss
> ---
Reviewed-by: Konrad Dybcio
Konrad
> drivers/gpu/drm/msm/dsi/dsi_cfg.c | 2 ++
> d
On 29.05.2023 11:44, Luca Weiss wrote:
> Add the nodes that describe the mdss so that display can work on
> MSM8226.
>
> Signed-off-by: Luca Weiss
> ---
> arch/arm/boot/dts/qcom-msm8226.dtsi | 118
>
> 1 file changed, 118 insertions(+)
>
> diff --git a/a
On 29/05/2023 12:44, Luca Weiss wrote:
Add the config for the v1.0.2 DSI found on MSM8226. We can reuse
existing bits from other revisions that are identical for v1.0.2.
Signed-off-by: Luca Weiss
---
drivers/gpu/drm/msm/dsi/dsi_cfg.c | 2 ++
drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 +
2 files
On 29/05/2023 15:10, Konrad Dybcio wrote:
On 29.05.2023 11:44, Luca Weiss wrote:
Add the nodes that describe the mdss so that display can work on
MSM8226.
Signed-off-by: Luca Weiss
---
arch/arm/boot/dts/qcom-msm8226.dtsi | 118
1 file changed, 118 inse
On 29.05.2023 14:19, Dmitry Baryshkov wrote:
> On 29/05/2023 15:10, Konrad Dybcio wrote:
>>
>>
>> On 29.05.2023 11:44, Luca Weiss wrote:
>>> Add the nodes that describe the mdss so that display can work on
>>> MSM8226.
>>>
>>> Signed-off-by: Luca Weiss
>>> ---
>>> arch/arm/boot/dts/qcom-msm82
On 29/05/2023 12:44, Luca Weiss wrote:
Add the required config for the v1.1 MDP5 found on MSM8226.
Signed-off-by: Luca Weiss
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 82
1 file changed, 82 insertions(+)
Reviewed-by: Dmitry Baryshkov
--
With best wis
On 29/05/2023 14:59, Konrad Dybcio wrote:
On 29.05.2023 11:44, Luca Weiss wrote:
Add the required config for the v1.1 MDP5 found on MSM8226.
Signed-off-by: Luca Weiss
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 82
1 file changed, 82 insertions(+)
diff
v7 -> v8:
- Fix up resume/suspend (icc now correctly parks to 0, don't abuse
OPP & genpd throughout system-wide suspend)
- Don't handle ebi1_clk separately, the bulk ops handle it just fine
- Rebase on next-20230525 (no meaningful changes)
v7:
https://lore.kernel.org/linux-arm-msm/20230223-topi
The "GMU Wrapper" is Qualcomm's name for "let's treat the GPU blocks
we'd normally assign to the GMU as if they were a part of the GMU, even
though they are not". It's a (good) software representation of the GMU_CX
and GMU_GX register spaces within the GPUSS that helps us programatically
treat thes
The "GMU Wrapper" is Qualcomm's name for "let's treat the GPU blocks
we'd normally assign to the GMU as if they were a part of the GMU, even
though they are not". It's a (good) software representation of the GMU_CX
and GMU_GX register spaces within the GPUSS that helps us programatically
treat thes
This function is responsible for telling the GPU to halt transactions
on all of its relevant buses, drain them and leave them in a predictable
state, so that the GPU can be e.g. reset cleanly.
Move the function to a6xx_gpu.c, remove the static keyword and add a
prototype in a6xx_gpu.h to accomodat
These two will be reused by at least A619_holi in the non-gmu
paths. Turn them non-static them to make it possible.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 4 ++--
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 2 ++
2 files changed, 4 ins
As pointed out by Akhil during the review process of GMU wrapper
introduction [1], it makes sense to move this write into the function
that's responsible for forcibly shutting the GMU off.
It is also very convenient to move this to GMU-specific code, so that
it does not have to be guarded by an if
Unify the indentation and explain the cryptic 0xF value.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 6bb4da
Introduce a6xx_gpu_sw_reset() in preparation for adding GMU wrapper
GPUs and reuse it in a6xx_gmu_force_off().
This helper, contrary to the original usage in GMU code paths, adds
a write memory barrier which together with the necessary delay should
ensure that the reset is never deasserted too qui
Rename lower_bit to hbb_lo and explain what it signifies.
Add explanations (wherever possible to other tunables).
Port setting min_access_length, ubwc_mode and hbb_hi from downstream.
Reviewed-by: Rob Clark
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 39 +++
Currently we're only deasserting REG_A6XX_RBBM_GBIF_HALT, but we also
need REG_A6XX_GBIF_HALT to be set to 0.
This is typically done automatically on successful GX collapse, but in
case that fails, we should take care of it.
Also, add a memory barrier to ensure it's gone through before jumping
to
Some (particularly SMD_RPM, a.k.a non-RPMh) SoCs implement A6XX GPUs
but don't implement the associated GMUs. This is due to the fact that
the GMU directly pokes at RPMh. Sadly, this means we have to take care
of enabling & scaling power rails, clocks and bandwidth ourselves.
Reuse existing Adreno
A610 and A619_holi don't support the feature. Disable it to make the GPU stop
crashing after almost each and every submission - the received data on
the GPU end was simply incomplete in garbled, resulting in almost nothing
being executed properly. Extend the disablement to adreno_has_gmu_wrapper,
a
A619_holi is a GMU-less variant of the already-supported A619 GPU.
It's present on at least SM4350 (holi) and SM6375 (blair). No mesa
changes are required. Add the required kernel-side support for it.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 27 +
Adreno 619 expects some tunables to be set differently. Make up for it.
Fixes: b7616b5c69e6 ("drm/msm/adreno: Add A619 support")
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff
A610 is implemented on at least three SoCs: SM6115 (bengal), SM6125
(trinket) and SM6225 (khaje). Trinket does not support speed binning
(only a single SKU exists) and we don't yet support khaje upstream.
Hence, add a fuse mapping table for bengal to allow for per-chip
frequency limiting.
Reviewed
Before transitioning to using per-SoC and not per-Adreno speedbin
fuse values (need another patchset to land elsewhere), a good
improvement/stopgap solution is to use adreno_is_aXYZ macros in
place of explicit revision matching. Do so to allow differentiating
between A619 and A619_holi.
Reviewed-b
A610 is one of (if not the) lowest-tier SKUs in the A6XX family. It
features no GMU, as it's implemented solely on SoCs with SMD_RPM.
What's more interesting is that it does not feature a VDDGX line
either, being powered solely by VDDCX and has an unfortunate hardware
quirk that makes its reset lin
A619_holi is implemented on at least two SoCs: SM4350 (holi) and SM6375
(blair). This is what seems to be a first occurrence of this happening,
but it's easy to overcome by guarding the SoC-specific fuse values with
of_machine_is_compatible(). Do just that to enable frequency limiting
on these SoCs
The GPU can only be one at a time. Turn a series of ifs into if +
elseifs to save some CPU cycles.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm
On Mon, May 29, 2023 at 11:43:59AM +0200, Luca Weiss wrote:
> Add the compatible for the DSI found on MSM8226.
>
> Signed-off-by: Luca Weiss
Acked-by: Conor Dooley
Thanks,
Conor.
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On Mon, May 29, 2023 at 11:44:00AM +0200, Luca Weiss wrote:
> Add the compatible for the MDP5 found on MSM8226.
>
> Signed-off-by: Luca Weiss
Acked-by: Conor Dooley
Thanks,
Conor.
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On Mon, May 29, 2023 at 11:43:58AM +0200, Luca Weiss wrote:
> The MSM8226 SoC uses a slightly different 28nm dsi phy. Add a new
> compatible for it.
>
> Signed-off-by: Luca Weiss
> ---
> Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml | 1 +
> Documentation/devicetree/bindings/di
Hi Thomas,
On Wed, May 24, 2023 at 11:21:38AM +0200, Thomas Zimmermann wrote:
> Many fbdev drivers use the same set of fb_ops helpers. Add Kconfig
> options to select them at once. This will help with making DRM's
> fbdev emulation code more modular, but can also be used to simplify
> fbdev's driv
On Wed, May 24, 2023 at 11:21:39AM +0200, Thomas Zimmermann wrote:
> For framebuffers in I/O and system memory, add macros that set
> struct fb_ops to the respective callback functions.
>
> For deferred I/O, add macros that generate callback functions with
> damage handling. Add initializer macros
On Wed, May 24, 2023 at 11:21:40AM +0200, Thomas Zimmermann wrote:
> Use the regular fbdev helpers for framebuffer I/O instead of DRM's
> helpers. Armada does not use damage handling, so DRM's fbdev helpers
> are mere wrappers around the fbdev code.
>
> By using fbdev helpers directly within each
Hi Thomas,
On Wed, May 24, 2023 at 11:21:50AM +0200, Thomas Zimmermann wrote:
> Implement dedicated fbdev helpers for framebuffer I/O instead
> of using DRM's helpers. Use an fbdev generator macro for
> deferred I/O to create the fbdev callbacks. i915 was the only
> caller of the DRM helpers, so r
Hi Thomas.
> v4:
> * use initializer and generator macros for struct fb_ops
> * partially support damage handling in msm (Dmitri)
I like the macros. They make it simpler and we do not spread the _cfb_
misname to more files.
> v3:
> * fix Kconfig options (Jingfeng)
> * mi
On Wed, May 24, 2023 at 11:21:48AM +0200, Thomas Zimmermann wrote:
> Export drm_fb_helper_damage() and drm_fb_helper_damage_range(), which
> handle damage areas for fbdev emulation. This is a temporary export
> that allows to move the DRM I/O helpers for fbdev into drivers. Only
> fbdev-generic and
Hi Thomas,
On Wed, May 24, 2023 at 11:21:50AM +0200, Thomas Zimmermann wrote:
> Implement dedicated fbdev helpers for framebuffer I/O instead
> of using DRM's helpers. Use an fbdev generator macro for
> deferred I/O to create the fbdev callbacks. i915 was the only
> caller of the DRM helpers, so r
On 2023-05-24 12:18:09, Abhinav Kumar wrote:
>
>
> On 5/24/2023 2:48 AM, Marijn Suijten wrote:
> > On 2023-05-23 13:01:13, Abhinav Kumar wrote:
> >>
> >>
> >> On 5/21/2023 10:21 AM, Dmitry Baryshkov wrote:
> >>> Drop SSPP-specifig debugfs register dumps in favour of using
> >>> debugfs/dri/0/kms
On 2023-05-26 12:09:45, Dmitry Baryshkov wrote:
> Currently the driver passes the PINGPONG index to
> dpu_hw_intf_ops::bind_pingpong_blk() callback and uses separate boolean
> flag to tell whether INTF should be bound or unbound. Simplify this by
> passing PINGPONG_NONE in case of unbinding and dro
On Tue, 30 May 2023 at 00:46, Marijn Suijten
wrote:
>
> On 2023-05-26 12:09:45, Dmitry Baryshkov wrote:
> > Currently the driver passes the PINGPONG index to
> > dpu_hw_intf_ops::bind_pingpong_blk() callback and uses separate boolean
> > flag to tell whether INTF should be bound or unbound. Simpli
On 24/05/2023 01:14, Melissa Wen wrote:
This series is a refined version of our RFC [1] for AMD driver-specific
color management properties. It is a collection of contributions from
Joshua, Harry and I to enhance AMD KMS color pipeline for Steam
Deck/SteamOS by exposing the large set of color cap
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