Switch to using the new DRM_AUX_BRIDGE helper to create the
transparent DRM bridge device instead of handcoding corresponding
functionality.
Acked-by: Vinod Koul
Signed-off-by: Dmitry Baryshkov
---
drivers/phy/qualcomm/Kconfig | 2 +-
drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 44
Switch to using the new DRM_AUX_BRIDGE helper to create the
transparent DRM bridge device instead of handcoding corresponding
functionality.
Reviewed-by: Heikki Krogerus
Acked-by: Greg Kroah-Hartman
Signed-off-by: Dmitry Baryshkov
---
drivers/usb/typec/mux/Kconfig | 2 +-
drivers/usb/typ
Define a helper for creating simple transparent bridges which serve the
only purpose of linking devices into the bridge chain up to the last
bridge representing the connector. This is especially useful for
DP/USB-C bridge chains, which can span across several devices, but do
not require any additio
[Resending since the discussion with Laurent has died with no response
received for more than three weeks]
Supporting DP/USB-C can result in a chain of several transparent
bridges (PHY, redrivers, mux, etc). All attempts to implement DP support
in a different way resulted either in series of hacks
As it was pointed out by Simon Ser, the DRM_MODE_CONNECTOR_USB connector
is reserved for the GUD devices. Other drivers (i915, amdgpu) use
DRM_MODE_CONNECTOR_DisplayPort even if the DP stream is handled by the
USB-C altmode. While we are still working on implementing the proper way
to let userspace
Add skips, fails and flakes for the SM8250 test.
Generated using update-xfails.py [1]
[1] https://patchwork.freedesktop.org/patch/561453/?series=124793&rev=1
Signed-off-by: Abhinav Kumar
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/ci/xfails/msm-sm8250-fails.txt | 29
Set CONFIG_INTERCONNECT_QCOM_SM8250 needs to =y so that the ASIX AX88179
USB Ethernet driver can be probed in time to set up nfsroot.
Signed-off-by: Abhinav Kumar
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/ci/arm64.config | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm
Recently, we've registered a Gitlab runner for a Qualcomm RB5 device that will
be
hosted and maintained in Qualcomm labs.
This series will add a corresponding CI job for testing SM8250 devices and add
the
skip/fails/flakes list. We were able to complete a successful run [1] with these
changes.
Add job for testing the Qualcomm RB5 board to CI. This will allow developers
working on MSM chipsets to test their changes on the SM8250 chipset.
This board shall be hosted and maintained by Qualcomm.
For now, keep the test a manual-run only. We will drop the tag after stabilizing
the tests and a
On 10/9/2023 3:32 AM, neil.armstr...@linaro.org wrote:
Hi Paloma,
On 28/07/2023 03:26, Paloma Arellano wrote:
Enable display compression (DSC v1.2) and CMD mode for 1080x2400 Visionox
VTDR6130 AMOLED DSI panel. In addition, this patch will set the default
to command mode with DSC enabled.
N
On 10/10/23 01:33, Richard Acayan wrote:
The Snapdragon 670 has a display subsystem for controlling and
outputting to the display. Add support for it in the device tree.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Richard Acayan
---
[...]
+ interconnects = <&mmss_n
Quoting Kuogee Hsieh (2023-10-06 15:55:03)
> The purpose of this patch series is to incorporate pm runtime framework
> into MSM eDP/DP driver so that eDP panel can be detected by DRM eDP panel
> driver during system probe time. During incorporating procedure, original
> customized pm realted fucnti
On 10/10/2023 10:10, Marijn Suijten wrote:
On 2023-10-09 18:36:11, Neil Armstrong wrote:
Starting with the SM8550 platform, the SSPP & WB Clock Controls are
no more in the MDP TOP registers, but in the SSPP & WB register space.
Add the corresponding SSPP & WB ops and use them from the vbif QoS
On 2023-10-09 18:36:11, Neil Armstrong wrote:
> Starting with the SM8550 platform, the SSPP & WB Clock Controls are
> no more in the MDP TOP registers, but in the SSPP & WB register space.
>
> Add the corresponding SSPP & WB ops and use them from the vbif QoS
> and OT limit setup functions.
>
> S
On 09/10/2023 19:10, Dmitry Baryshkov wrote:
On 09/10/2023 19:36, Neil Armstrong wrote:
The SM8550 has the SSPP clk_ctrl in the SSPP registers, move them
out of the MDP top.
Signed-off-by: Neil Armstrong
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 35 ++
1 f
On 09/10/2023 19:10, Dmitry Baryshkov wrote:
On 09/10/2023 19:36, Neil Armstrong wrote:
The SM8550 has the SSPP clk_ctrl in the SSPP registers, move them
out of the MDP top.
Signed-off-by: Neil Armstrong
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 35 ++
1 f
On 09/10/2023 19:07, Dmitry Baryshkov wrote:
On 09/10/2023 19:36, Neil Armstrong wrote:
Now clk_ctrl IDs can be optional and the clk_ctrl_reg can be specified
on the SSPP & WB caps directly, pass the SSPP & WB hw struct to the
qos & limit params then call the clk_force_ctrl() op accordingly.
Si
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