From: Zan Dobersek
In addition to the CP_PERFCTR_CP_SEL register range, allow writes to the
CP_BV_PERFCTR_CP_SEL registers in the 0x8e0-0x8e6 range for profiling
purposes of tools like fdperf and perfetto.
Signed-off-by: Zan Dobersek
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 5 +++--
1 file
From: Rob Clark
[ Upstream commit 917e9b7c2350e3e53162fcf5035e5f2d68e2cbed ]
This reverts commit abe2023b4cea192ab266b351fd38dc9dbd846df0.
Changing the locking order means that scheduler/msm_job_run() can race
with the recovery kthread worker, with the result that the GPU gets an
extra runpm ge
From: Rob Clark
[ Upstream commit 917e9b7c2350e3e53162fcf5035e5f2d68e2cbed ]
This reverts commit abe2023b4cea192ab266b351fd38dc9dbd846df0.
Changing the locking order means that scheduler/msm_job_run() can race
with the recovery kthread worker, with the result that the GPU gets an
extra runpm ge
Hi Dave,
This is the main pull for v6.9, description below.
We may have a second smaller pull next week for CDM support, which
depends on a patch in drm-misc-next which was just recently tagged.
The following changes since commit 41c177cf354126a22443b5c80cec9fdd313e67e1:
Merge tag 'drm-misc-n