On Sat, 15 Jun 2024 00:58:51 +0300, Danila Tikhonov wrote:
> This series adds MDSS and DPU support for SM7150.
>
> Changes in v3:
> - Swap DPU and MDSS patches (Krzysztof)
> - Add an explanation of the abbreviation DPU in patch 1 (Krzysztof)
> - Switch qseed3_1_4 on qseed3_2_4 in patch 2 (Dmitry
On Thu, 13 Jun 2024 20:05:03 +0300, Dmitry Baryshkov wrote:
> Command-mode DSI panels need to signal the display controlller when
> vsync happens, so that the device can start sending the next frame. Some
> devices (Google Pixel 3) use a non-default pin, so additional
> configuration is required.
On Fri, 07 Jun 2024 16:22:57 +0300, Dmitry Baryshkov wrote:
> This patchset sits on top Maxime's HDMI connector patchset ([1]).
>
> Currently this is an RFC exploring the interface between HDMI bridges
> and HDMI connector code. This has been lightly verified on the Qualcomm
> DB820c, which has
On Thu, 30 May 2024 13:56:44 +0800, Jun Nie wrote:
> This is follow up update to Jonathan's patch set.
>
> Changes vs V5:
> - Add hardware version check for compression bit change in cfg2 register
>
> Changes vs V4:
> - Polish width calculation with helper function
> - Split cfg2 compression bi
On Thu, 20 Jun 2024 13:17:30 -0700, Abhinav Kumar wrote:
> clear_pending_flush() ctl op is always assigned irrespective of the DPU
> hardware revision. Hence there is no needed to check whether the op has
> been assigned before calling it.
>
> Drop the checks across the driver for clear_pending_
On Tue, 23 Apr 2024 00:36:58 +0200, Konrad Dybcio wrote:
> Shaving off some cruft
>
> obj files seem to be identical pre and post cleanup which is always
> a good sign
>
>
Applied, thanks!
[1/2] drm/msm/dsi: Remove dsi_phy_read/write()
https://gitlab.freedesktop.org/lumag/msm/-/commit/
On Thu, 09 May 2024 19:52:04 +0200, Barnabás Czémán wrote:
> CTLs on older qualcomm SOCs like msm8953 and msm8996 has not got interrupts,
> so better to skip CTL irq callback register/unregister
> make dpu_ctl_cfg be able to define without intr_start.
>
>
Applied, thanks!
[1/1] drm/msm/dpu: g
On 23/06/2024 01:25, Barnabás Czémán wrote:
> Add the compatible for the MDP5 found on MSM8937.
>
> Signed-off-by: Barnabás Czémán
> ---
Reviewed-by: Krzysztof Kozlowski
---
This is an automated instruction, just in case, because many review tags
are being ignored. If you know the process,
On 23/06/2024 01:25, Barnabás Czémán wrote:
> The MSM8937 SoC uses a slightly different 28nm dsi phy. Add a new
> compatible for it.
>
> Signed-off-by: Barnabás Czémán
> ---
Reviewed-by: Krzysztof Kozlowski
Best regards,
Krzysztof
On Sun, Jun 23, 2024 at 7:59 AM Dmitry Baryshkov
wrote:
>
> On Sun, Jun 23, 2024 at 01:25:52AM GMT, Barnabás Czémán wrote:
> > From: Daniil Titov
> >
> > Add the mdp5_cfg_hw entry for MDP5 version v1.14 found on msm8937.
> >
> > Signed-off-by: Daniil Titov
> > Signed-off-by: Barnabás Czémán
> >
This series adds support for the Adreno X1-85 GPU found in Qualcomm's
compute series chipset, Snapdragon X1 Elite (x1e80100). In this new
naming scheme for Adreno GPU, 'X' stands for compute series, '1' denotes
1st generation and '8' & '5' denotes the tier and the SKU which it
belongs.
X1-85 has m
Document Adreno X185 GMU in the dt-binding specification.
Signed-off-by: Akhil P Oommen
---
Documentation/devicetree/bindings/display/msm/gmu.yaml | 4
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml
b/Documentation/devicetree/bindings/
Add support in drm/msm driver for the Adreno X185 gpu found in
Snapdragon X1 Elite chipset.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 19 +++
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 ++
drivers/gpu/drm/msm/adreno/adreno_device.c |
Add the necessary dt nodes for gpu support in X1E80100.
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 195 +
1 file changed, 195 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
inde
On 23/06/2024 13:06, Akhil P Oommen wrote:
> This series adds support for the Adreno X1-85 GPU found in Qualcomm's
> compute series chipset, Snapdragon X1 Elite (x1e80100). In this new
> naming scheme for Adreno GPU, 'X' stands for compute series, '1' denotes
> 1st generation and '8' & '5' denotes
On 23/06/2024 13:06, Akhil P Oommen wrote:
> Document Adreno X185 GMU in the dt-binding specification.
>
> Signed-off-by: Akhil P Oommen
> ---
>
> Documentation/devicetree/bindings/display/msm/gmu.yaml | 4
Reviewed-by: Krzysztof Kozlowski
Best regards,
Krzysztof
On 23/06/2024 13:06, Akhil P Oommen wrote:
> Add the necessary dt nodes for gpu support in X1E80100.
>
> Signed-off-by: Akhil P Oommen
> ---
> + gmu: gmu@3d6a000 {
> + compatible = "qcom,adreno-gmu-x185.1",
> "qcom,adreno-gmu";
> + reg = <0x0 0
We expect each schema with variable number of clocks, to have the widest
constrains in top-level "properties:". This is more readable and also
makes binding stricter, if there is no "if:then:" block for given
variant.
Signed-off-by: Krzysztof Kozlowski
---
Documentation/devicetree/bindings/disp
All devices should (and actually do) have same order of entries, if
possible. That's the case for reg/reg-names, so define the reg-names in
top-level to enforce that.
Signed-off-by: Krzysztof Kozlowski
---
Documentation/devicetree/bindings/display/msm/gpu.yaml | 5 -
1 file changed, 4 inser
MMIO address space is known per each variant of Adreno GPU, so we can
constrain the reg/reg-names entries for each variant. There is no DTS
for A619, so that part is not accurate but could be corrected later.
Signed-off-by: Krzysztof Kozlowski
---
.../devicetree/bindings/display/msm/gpu.yaml |
On Sun, Jun 23, 2024 at 01:17:16PM +0200, Krzysztof Kozlowski wrote:
> On 23/06/2024 13:06, Akhil P Oommen wrote:
> > Add the necessary dt nodes for gpu support in X1E80100.
> >
> > Signed-off-by: Akhil P Oommen
> > ---
> > + gmu: gmu@3d6a000 {
> > + compatible = "qcom
On 23/06/2024 13:06, Akhil P Oommen wrote:
> Document Adreno X185 GMU in the dt-binding specification.
>
> Signed-off-by: Akhil P Oommen
> ---
>
> Documentation/devicetree/bindings/display/msm/gmu.yaml | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/Documentation/devicetree/bindin
On 23/06/2024 14:28, Akhil P Oommen wrote:
> On Sun, Jun 23, 2024 at 01:17:16PM +0200, Krzysztof Kozlowski wrote:
>> On 23/06/2024 13:06, Akhil P Oommen wrote:
>>> Add the necessary dt nodes for gpu support in X1E80100.
>>>
>>> Signed-off-by: Akhil P Oommen
>>> ---
>>> + gmu: gmu@3d6a000
dtschema v2024.4, v2024.5 and maybe earlier do not select device nodes for
given binding validation if the schema contains compatible list with
pattern and a const fallback. This leads to binding being a no-op - not
being applied at all. Issue should be fixed in the dtschema but for now
add a wor
On Sun, Jun 23, 2024 at 02:00:26PM +0200, Krzysztof Kozlowski wrote:
> MMIO address space is known per each variant of Adreno GPU, so we can
> constrain the reg/reg-names entries for each variant. There is no DTS
> for A619, so that part is not accurate but could be corrected later.
>
> Signed-of
On Sun, Jun 23, 2024 at 02:00:25PM +0200, Krzysztof Kozlowski wrote:
> All devices should (and actually do) have same order of entries, if
> possible. That's the case for reg/reg-names, so define the reg-names in
> top-level to enforce that.
>
> Signed-off-by: Krzysztof Kozlowski
Acked-by: Cono
On Sun, Jun 23, 2024 at 02:00:24PM +0200, Krzysztof Kozlowski wrote:
> We expect each schema with variable number of clocks, to have the widest
> constrains in top-level "properties:". This is more readable and also
> makes binding stricter, if there is no "if:then:" block for given
> variant.
>
On Sun, Jun 23, 2024 at 02:53:17PM +0200, Krzysztof Kozlowski wrote:
> On 23/06/2024 14:28, Akhil P Oommen wrote:
> > On Sun, Jun 23, 2024 at 01:17:16PM +0200, Krzysztof Kozlowski wrote:
> >> On 23/06/2024 13:06, Akhil P Oommen wrote:
> >>> Add the necessary dt nodes for gpu support in X1E80100.
>
On 23/06/2024 16:13, Conor Dooley wrote:
> On Sun, Jun 23, 2024 at 02:00:26PM +0200, Krzysztof Kozlowski wrote:
>> MMIO address space is known per each variant of Adreno GPU, so we can
>> constrain the reg/reg-names entries for each variant. There is no DTS
>> for A619, so that part is not accurat
Commit f30ac26def18 ("arm64: dts: qcom: add sm8150 GPU nodes") re-used
amd,imageon compatible for the SM8150 just to enable headless mode due
to missing display controller nodes. This work-around was later
narrowed to the SM8150 MTP board in commit 1642ab96efa4 ("arm64: dts:
qcom: sm8150: Don't st
The SM8150 MTP board does not have magically different GPU than the
SM8150, so it cannot use amd,imageon compatible, also pointed by
dtbs_check:
sm8150-mtp.dtb: gpu@2c0: compatible: 'oneOf' conditional failed, one must
be fixed:
['qcom,adreno-640.1', 'qcom,adreno', 'amd,imageon'] is too
devicetree/bindings/display/msm/gpu.yaml | 27 ++
1 file changed, 23 insertions(+), 4 deletions(-)
---
base-commit: d47fa80a484f97ea51991c9547636a799c264652
change-id: 20240623-qcom-adreno-dts-bindings-driver-87521a145260
Best regards,
--
Krzysztof Kozlowski
We expect each schema with variable number of clocks, to have the widest
constrains in top-level "properties:". This is more readable and also
makes binding stricter, if there is no "if:then:" block for given
variant.
Acked-by: Conor Dooley
Signed-off-by: Krzysztof Kozlowski
---
Documentation/
Regex for newer Adreno compatibles can be simpler.
Suggested-by: Conor Dooley
Signed-off-by: Krzysztof Kozlowski
---
Documentation/devicetree/bindings/display/msm/gpu.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml
All devices should (and actually do) have same order of entries, if
possible. That's the case for reg/reg-names, so define the reg-names in
top-level to enforce that.
Acked-by: Conor Dooley
Signed-off-by: Krzysztof Kozlowski
---
Documentation/devicetree/bindings/display/msm/gpu.yaml | 5 -
dtschema v2024.4, v2024.5 and maybe earlier do not select device nodes for
given binding validation if the schema contains compatible list with
pattern and a const fallback. This leads to binding being a no-op - not
being applied at all. Issue should be fixed in the dtschema but for now
add a wor
On 23/06/2024 17:16, Akhil P Oommen wrote:
> On Sun, Jun 23, 2024 at 02:53:17PM +0200, Krzysztof Kozlowski wrote:
>> On 23/06/2024 14:28, Akhil P Oommen wrote:
>>> On Sun, Jun 23, 2024 at 01:17:16PM +0200, Krzysztof Kozlowski wrote:
On 23/06/2024 13:06, Akhil P Oommen wrote:
> Add the nece
This patch series adds support for the MDP and DSI PHY as found on the
MSM8937 platform.
Signed-off-by: Barnabás Czémán
---
Changes in v2:
- Remove MDP_CAP_SRC_SPLIT from mdp5_cfg
- Link to v1: https://lore.kernel.org/r/20240623-dsi-v1-0-4ab560eb5...@gmail.com
---
Barnabás Czémán (2):
dt
Add the compatible for the MDP5 found on MSM8937.
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Barnabás Czémán
---
Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml
b/
From: Daniil Titov
Add the mdp5_cfg_hw entry for MDP5 version v1.14 found on msm8937.
Signed-off-by: Daniil Titov
Signed-off-by: Barnabás Czémán
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 88
1 file changed, 88 insertions(+)
diff --git a/drivers/gpu/drm/m
The MSM8937 SoC uses a slightly different 28nm dsi phy. Add a new
compatible for it.
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Barnabás Czémán
---
Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml | 1 +
Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml| 1 +
From: Daniil Titov
Add phy configuration for 28nm dsi phy found on MSM8937 SoC. Only
difference from existing msm8916 configuration is number of phy
and io_start addresses.
Signed-off-by: Daniil Titov
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Barnabás Czémán
---
drivers/gpu/drm/msm/dsi/ph
On Sun, Jun 23, 2024 at 08:46:30PM GMT, Akhil P Oommen wrote:
> On Sun, Jun 23, 2024 at 02:53:17PM +0200, Krzysztof Kozlowski wrote:
> > On 23/06/2024 14:28, Akhil P Oommen wrote:
> > > On Sun, Jun 23, 2024 at 01:17:16PM +0200, Krzysztof Kozlowski wrote:
> > >> On 23/06/2024 13:06, Akhil P Oommen w
On Sun, Jun 23, 2024 at 03:40:06PM -0500, Bjorn Andersson wrote:
> On Sun, Jun 23, 2024 at 08:46:30PM GMT, Akhil P Oommen wrote:
> > On Sun, Jun 23, 2024 at 02:53:17PM +0200, Krzysztof Kozlowski wrote:
> > > On 23/06/2024 14:28, Akhil P Oommen wrote:
> > > > On Sun, Jun 23, 2024 at 01:17:16PM +0200
On Sun, Jun 23, 2024 at 12:48:53PM GMT, Barnabás Czémán wrote:
> On Sun, Jun 23, 2024 at 7:59 AM Dmitry Baryshkov
> wrote:
> >
> > On Sun, Jun 23, 2024 at 01:25:52AM GMT, Barnabás Czémán wrote:
> > > From: Daniil Titov
> > >
> > > Add the mdp5_cfg_hw entry for MDP5 version v1.14 found on msm8937.
On Sun, Jun 23, 2024 at 04:36:29PM GMT, Akhil P Oommen wrote:
> Add support in drm/msm driver for the Adreno X185 gpu found in
> Snapdragon X1 Elite chipset.
>
> Signed-off-by: Akhil P Oommen
> ---
>
> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 19 +++
> drivers/gpu/drm/msm/ad
On Sun, Jun 23, 2024 at 04:36:30PM GMT, Akhil P Oommen wrote:
> Add the necessary dt nodes for gpu support in X1E80100.
>
> Signed-off-by: Akhil P Oommen
> ---
>
> arch/arm64/boot/dts/qcom/x1e80100.dtsi | 195 +
> 1 file changed, 195 insertions(+)
>
> diff --git a/arch/
On Sun, Jun 23, 2024 at 01:11:48PM GMT, Krzysztof Kozlowski wrote:
> On 23/06/2024 13:06, Akhil P Oommen wrote:
> > This series adds support for the Adreno X1-85 GPU found in Qualcomm's
> > compute series chipset, Snapdragon X1 Elite (x1e80100). In this new
> > naming scheme for Adreno GPU, 'X' sta
On Sun, Jun 23, 2024 at 10:30:37PM GMT, Barnabás Czémán wrote:
> From: Daniil Titov
>
> Add the mdp5_cfg_hw entry for MDP5 version v1.14 found on msm8937.
>
> Signed-off-by: Daniil Titov
> Signed-off-by: Barnabás Czémán
> ---
> drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 88
>
Remove MDP_CAP_SRC_SPLIT from msm8x53_config because
it is not referenced in downstream.
Fixes: fb25d4474fa0 ("drm/msm/mdp5: Add configuration for MDP v1.16")
Signed-off-by: Barnabás Czémán
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff
On Sun, Jun 23, 2024 at 01:11:48PM +0200, Krzysztof Kozlowski wrote:
> On 23/06/2024 13:06, Akhil P Oommen wrote:
> > This series adds support for the Adreno X1-85 GPU found in Qualcomm's
> > compute series chipset, Snapdragon X1 Elite (x1e80100). In this new
> > naming scheme for Adreno GPU, 'X' s
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