On Mon, Oct 14, 2024 at 01:23:24PM -0700, Jessica Zhang wrote:
>
>
> On 10/14/2024 12:13 AM, Dmitry Baryshkov wrote:
> > On Sun, Oct 13, 2024 at 07:37:20PM -0700, Abhinav Kumar wrote:
> > > Hi Dmitry
> > >
> > > On 10/13/2024 5:20 PM, Dmitry Baryshkov
@quicinc.com
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
On Tue, 15 Oct 2024 at 11:27, Jun Nie wrote:
>
> Dmitry Baryshkov 于2024年10月11日周五 15:13写道：
> >
> > On Fri, 11 Oct 2024 at 10:11, Jun Nie wrote:
> > >
> > > Dmitry Baryshkov 于2024年10月11日周五 15:03写道：
> > > >
> > > > On Fri, 11 Oct 2024 at
On Tue, 15 Oct 2024 at 10:02, Soutrik Mukhopadhyay
wrote:
>
>
> On 10/6/2024 8:30 PM, Dmitry Baryshkov wrote:
> > On Fri, 4 Oct 2024 at 12:30, Soutrik Mukhopadhyay
> > wrote:
> >> This series adds support for the DisplayPort controller
> >> and eDP PHY v5
On Sun, Oct 13, 2024 at 07:37:20PM -0700, Abhinav Kumar wrote:
> Hi Dmitry
>
> On 10/13/2024 5:20 PM, Dmitry Baryshkov wrote:
> > On Fri, Oct 11, 2024 at 10:25:13AM -0700, Jessica Zhang wrote:
> > > Only enable the merge_3d block for the video phys encoder when the 3d
On Fri, Oct 11, 2024 at 10:25:13AM -0700, Jessica Zhang wrote:
> Only enable the merge_3d block for the video phys encoder when the 3d
> blend mode is not *_NONE since there is no need to activate the merge_3d
> block for cases where merge_3d is not needed.
>
> Fixes: 3e79527a33a8 ("drm/msm/dpu: e
On Fri, 11 Oct 2024 at 11:13, Jun Nie wrote:
>
> Dmitry Baryshkov 于2024年10月10日周四 21:29写道：
> >
> > On Wed, Oct 09, 2024 at 04:50:25PM GMT, Jun Nie wrote:
> > > Clip plane into pipes per left and right half screen ROI if topology
> > > is quad pipe.
> >
On Fri, 11 Oct 2024 at 10:18, Jun Nie wrote:
>
> Dmitry Baryshkov 于2024年10月11日周五 15:10写道：
> >
> > On Fri, 11 Oct 2024 at 09:49, Jun Nie wrote:
> > >
> > > Dmitry Baryshkov 于2024年10月10日周四 21:08写道：
> > > >
> > > > On Wed, Oct 09, 202
On Fri, 11 Oct 2024 at 10:11, Jun Nie wrote:
>
> Dmitry Baryshkov 于2024年10月11日周五 15:03写道：
> >
> > On Fri, 11 Oct 2024 at 09:40, Jun Nie wrote:
> > >
> > > Dmitry Baryshkov 于2024年10月10日周四 21:15写道：
> > > >
> > > > On Wed, Oct 09, 202
On Fri, 11 Oct 2024 at 09:49, Jun Nie wrote:
>
> Dmitry Baryshkov 于2024年10月10日周四 21:08写道：
> >
> > On Wed, Oct 09, 2024 at 04:50:18PM GMT, Jun Nie wrote:
> > > Store pipes in array with removing dedicated r_pipe. There are
> > > 2 pipes in a drm plane
On Fri, 11 Oct 2024 at 09:30, Jun Nie wrote:
>
> Dmitry Baryshkov 于2024年10月10日周四 21:12写道：
> >
> > On Wed, Oct 09, 2024 at 04:50:21PM GMT, Jun Nie wrote:
> > > Update mixer number info earlier so that the plane nopipe check
> > > can have the info to clip the
On Fri, 11 Oct 2024 at 09:40, Jun Nie wrote:
>
> Dmitry Baryshkov 于2024年10月10日周四 21:15写道：
> >
> > On Wed, Oct 09, 2024 at 04:50:22PM GMT, Jun Nie wrote:
> > > Blend pipes by set of mixer pair config. The first 2 pipes are for left
> > > half screen with the
On Fri, 11 Oct 2024 at 09:54, Jun Nie wrote:
>
> Dmitry Baryshkov 于2024年10月10日周四 21:21写道：
> >
> > On Wed, Oct 09, 2024 at 04:50:24PM GMT, Jun Nie wrote:
> > > Share SSPP info for multi-rect case if virtual plane is not enabled.
> > > Otherwise, the 2nd half of
On Wed, Oct 09, 2024 at 08:41:13PM GMT, Jessica Zhang wrote:
> Don't set the merge_3d pending flush bits if the mode_3d is
> BLEND_3D_NONE.
>
> Always flushing merge_3d can cause timeout issues when there are
> multiple commits with concurrent writeback enabled.
>
> This is because the video phys
On Wed, Oct 09, 2024 at 04:50:27PM GMT, Jun Nie wrote:
> Request 4 mixers and 4 DSC for the case that both dual-DSI and DSC are
> enabled. We prefer to use 4 pipes for dual DSI case for it is power optimal
> for DSC.
>
> Signed-off-by: Jun Nie
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
On Wed, Oct 09, 2024 at 04:50:26PM GMT, Jun Nie wrote:
> Support SSPP assignment for quad-pipe case with unified method.
> The first 2 pipes can share a set of mixer config and enable
> multi-rect mode if condition is met. It is also the case for
> the later 2 pipes.
>
> Signed-off-by: Jun Nie
>
On Wed, Oct 09, 2024 at 04:50:25PM GMT, Jun Nie wrote:
> Clip plane into pipes per left and right half screen ROI if topology
> is quad pipe.
Why? Please provide an explanation for the reviewers not knowing the
details.
> Then split the clipped rectangle by half if the rectangle
> width still exc
On Wed, Oct 09, 2024 at 04:50:24PM GMT, Jun Nie wrote:
> Share SSPP info for multi-rect case if virtual plane is not enabled.
> Otherwise, the 2nd half of DMA content is not displayed due to sspp
> pointer of r_pipe is null.
Fixes?
>
> Signed-off-by: Jun Nie
> ---
> drivers/gpu/drm/msm/disp/dp
On Wed, Oct 09, 2024 at 04:50:23PM GMT, Jun Nie wrote:
> Move requreiment check to routine of every pipe check. Because there is
s/Because there is/There will be/
> multiple SSPPs for quad-pipe case in future.
>
> Signed-off-by: Jun Nie
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 2
On Wed, Oct 09, 2024 at 04:50:22PM GMT, Jun Nie wrote:
> Blend pipes by set of mixer pair config. The first 2 pipes are for left
> half screen with the first set of mixer pair config. And the later 2 pipes
> are for right in quad pipe case.
>
> Signed-off-by: Jun Nie
> ---
> drivers/gpu/drm/msm/
On Wed, Oct 09, 2024 at 04:50:21PM GMT, Jun Nie wrote:
> Update mixer number info earlier so that the plane nopipe check
> can have the info to clip the plane. Otherwise, the first nonpipe
> check will have mixer number as 0 and plane is not checked.
>
> Signed-off-by: Jun Nie
> ---
> drivers/gp
On Wed, Oct 09, 2024 at 04:50:20PM GMT, Jun Nie wrote:
> There are 2 interfaces and 4 pingpong in quad pipe. Map the 2nd
> interface to 3rd PP instead of the 2nd PP.
>
> Signed-off-by: Jun Nie
Reviewed-by: Dmitry Baryshkov
> ---
> drivers/gpu/drm/msm/disp/dpu1/
On Wed, Oct 09, 2024 at 04:50:18PM GMT, Jun Nie wrote:
> Store pipes in array with removing dedicated r_pipe. There are
> 2 pipes in a drm plane at most currently. While 4 pipes are
> needed for new usage case. This change generalize the handling
> to pipe pair and ease handling to another pipe pai
On Wed, Oct 09, 2024 at 04:50:14PM GMT, Jun Nie wrote:
> Add resource allocation type info.
Please describe changes properly.
>
> Signed-off-by: Jun Nie
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 23 +++
> 1 file changed, 19 insertions(+), 4 deletions(-)
>
> diff --g
On Wed, Oct 09, 2024 at 04:50:13PM GMT, Jun Nie wrote:
>
> ---
> 2 or more SSPPs and dual-DSI interface are need for super wide DSI panel.
> And 4 DSC are prefered for power optimal in this case. This patch set
> extend number of pipes to 4 and revise related mixer blending logic
> to support quad
On Wed, Oct 09, 2024 at 02:38:43PM GMT, Jun Nie wrote:
> Only 2 DSC engines are allowed, or no DSC is involved currently.
> We need 4 DSC in quad-pipe topology in future. So let's only configure
> DSC engines in use, instread of maximum number of DSC engines.
>
> Signed-off-by: Jun Nie
> ---
> d
On Thu, 10 Oct 2024 at 06:46, Jessica Zhang wrote:
>
> Only program the merge_3d block for the video phys encoder when the 3d
> blend mode is not NONE
Please describe why, not what.
>
> Fixes: 3e79527a33a8 ("drm/msm/dpu: enable merge_3d support on sm8150/sm8250")
> Suggested-by: Abhinav Kumar
>
On Thu, 10 Oct 2024 at 04:47, Jun Nie wrote:
>
> Dmitry Baryshkov 于2024年10月10日周四 06:10写道：
> >
> > On Wed, 9 Oct 2024 at 09:39, Jun Nie wrote:
> > >
> > > Only 2 DSC engines are allowed, or no DSC is involved currently.
> >
> > Can't parse
On Wed, 9 Oct 2024 at 17:34, Mahadevan wrote:
>
> This series introduces support to enable the Mobile Display Subsystem (MDSS)
> and Display Processing Unit (DPU) for the Qualcomm SA8775P target. It
> includes the addition of the hardware catalog, compatible string,
> relevant device tree changes,
On Wed, 9 Oct 2024 at 09:39, Jun Nie wrote:
>
> Only 2 DSC engines are allowed, or no DSC is involved currently.
Can't parse this phrase.
> We need 4 DSC in quad-pipe topology in future. So let's only configure
> DSC engines in use, instread of maximum number of DSC engines.
Nit: instead
>
> S
-LLCC and LLCC-EBI paths.
Fixes: 10e024671295 ("arm64: dts: qcom: sm8650: add interconnect dependent
device nodes")
Cc: sta...@kernel.org
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sm8650.dtsi | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/arch/
-LLCC and LLCC-EBI paths.
Fixes: d7da51db5b81 ("arm64: dts: qcom: sm8550: add display hardware devices")
Cc: sta...@kernel.org
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boo
paths (and LLCC-EBI should not be a part of such
division).
Drop mdp1-mem paths and use MDP-EBI path directly.
Signed-off-by: Dmitry Baryshkov
---
Dmitry Baryshkov (2):
arm64: dts: qcom: sm8550: correct MDSS interconnects
arm64: dts: qcom: sm8650: correct MDSS interconnects
arch
k
> ---
> drivers/gpu/drm/msm/dsi/dsi_host.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
m/dsi/dsi_host.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
On Mon, Sep 30, 2024 at 08:35:59PM GMT, Barnabás Czémán wrote:
> From: Dmitry Baryshkov
>
> Add support for MSM8917, which has MDP5 v1.15. It looks like
> trimmed down version of MSM8937. Even fewer PP, LM and no DSI1.
>
> Signed-off-by: Dmitry Baryshkov
> [Remove intr_s
On Mon, Sep 30, 2024 at 08:35:58PM GMT, Barnabás Czémán wrote:
> From: Dmitry Baryshkov
>
> Add support for MSM8937, which has MDP5 v1.14. It looks like
> trimmed down version of MSM8996. Less SSPP, LM and PP blocks. No DSC,
> etc.
>
> Signed-off-by: Dmitry Baryshkov
>
On Mon, Sep 30, 2024 at 08:35:57PM GMT, Barnabás Czémán wrote:
> From: Dmitry Baryshkov
>
> Add support for MSM8953, which has MDP5 v1.16. It looks like
> trimmed down version of MSM8996. Less SSPP, LM and PP blocks. No DSC,
> etc.
>
> Signed-off-by: Dmitry Baryshkov
>
provided.
>
> Signed-off-by: Konrad Dybcio
> Signed-off-by: Konrad Dybcio
> [DB: rebased on top of sblk changes, add dpu_rgb_sblk]
> Signed-off-by: Dmitry Baryshkov
> Acked-by: Konrad Dybcio
> [Removed intr_start from CTLs config, removed LM_3 and LM_4]
> Sig
s/qcom/sa8775p.dtsi | 89
> +++
> 1 file changed, 89 insertions(+)
>
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
On Tue, Oct 01, 2024 at 12:11:39PM GMT, Mahadevan via B4 Relay wrote:
> From: Mahadevan
>
> Add definitions for the display hardware used on the
> Qualcomm SA8775P platform.
>
> Reviewed-by: Dmitry Baryshkov
> Signed-off-by: Mahadevan
> ---
> .../drm/msm/disp/dpu
e changed, 11 insertions(+)
>
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
MDSS0 DPTX0 and DPTX1 have been conducted.
>
> Reviewed-by: Dmitry Baryshkov
> Signed-off-by: Soutrik Mukhopadhyay
> ---
> v2: No change
>
> v3: Fixed review comments from Konrad and Bjorn
> -Added all the necessary DPTX controllers for this platform.
>
> v4:
On Sat, Oct 05, 2024 at 10:38:10AM GMT, Jonathan Marek wrote:
> When (mode->clock * 1000) is larger than (1<<31), int to unsigned long
> conversion will sign extend the int to 64 bits and the pclk_rate value
> will be incorrect.
>
> Fix this by making the result of the multiplication unsigned.
>
On Sat, Oct 05, 2024 at 10:38:09AM GMT, Jonathan Marek wrote:
> drm_mode_vrefresh() can introduce a large rounding error, avoid it.
>
Fixes?
> Signed-off-by: Jonathan Marek
> ---
> drivers/gpu/drm/msm/dsi/dsi_host.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/driv
On Fri, 4 Oct 2024 at 12:30, Soutrik Mukhopadhyay
wrote:
>
> This series adds support for the DisplayPort controller
> and eDP PHY v5 found on the Qualcomm SA8775P platform.
>
> ---
> v2: Fixed review comments from Dmitry and Bjorn
> - Made aux_cfg array as const.
> - Reused edp_sw
On October 1, 2024 1:16:31 PM GMT+03:00, Krzysztof Kozlowski
wrote:
>On 01/10/2024 08:41, Mahadevan via B4 Relay wrote:
>> This series introduces support to enable the Mobile Display Subsystem (MDSS)
>> and Display Processing Unit (DPU) for the Qualcomm SA8775P target. It
>> includes the addition
On Fri, 27 Sept 2024 at 17:39, wrote:
>
> On 2024-08-01 21:25, Dmitry Baryshkov wrote:
> > On Fri, Jun 28, 2024 at 04:39:38PM GMT, Barnabás Czémán wrote:
> >> This patch series add dpu support for MSM8996/MSM8953 devices.
> >>
> >> Note, by default these
On Fri, 27 Sept 2024 at 17:44, wrote:
>
> On 2024-08-18 09:16, Icenowy Zheng wrote:
> > 在 2024-06-28星期五的 16:39 +0200，Barnabás Czémán写道：
> >> From: Konrad Dybcio
> >>
> >> Add support for MSM8996, which - fun fact - was the SoC that this
> >> driver
> >> (or rather SDE, its downstream origin) was
On Fri, Sep 27, 2024 at 12:14:16PM GMT, Mahadevan P wrote:
>
> On 9/26/2024 6:32 PM, Dmitry Baryshkov wrote:
> > On Thu, Sep 26, 2024 at 04:31:35PM GMT, Mahadevan wrote:
> > > Add Mobile Display Subsystem (MDSS) support for the SA8775P platform.
> > >
On Thu, Sep 26, 2024 at 04:31:37PM GMT, Mahadevan wrote:
> Add mdss0 and mdp devicetree nodes for sa8775p target.
>
> Signed-off-by: Mahadevan
>
> ---
>
> This patch depends on the clock enablement change:
> https://lore.kernel.org/all/20240816-sa8775p-mm-v3-v1-0-77d53c3c0...@quicinc.com/
>
>
On Thu, Sep 26, 2024 at 04:31:36PM GMT, Mahadevan wrote:
> Add definitions for the display hardware used on the
> Qualcomm SA8775P platform.
>
> Signed-off-by: Mahadevan
> ---
Reviewed-by: Dmitry Baryshkov
Minor nit below.
> [v2]
> - Reorder compatible string of DPU
On Thu, Sep 26, 2024 at 04:31:35PM GMT, Mahadevan wrote:
> Add Mobile Display Subsystem (MDSS) support for the SA8775P platform.
>
> Signed-off-by: Mahadevan
> ---
>
> [v2]
> - Update commit message. [Dmitry]
> - Reorder compatible string of MDSS based on alphabetical order. [Dmitry]
> - add reg
On Thu, Sep 26, 2024 at 04:31:34PM GMT, Mahadevan wrote:
> Document the DPU for Qualcomm SA8775P platform.
>
> Signed-off-by: Mahadevan
> ---
>
> [v2]
> - Use fake DISPCC nodes to avoid clock dependencies in dt-bindings. [Dmitry]
> - Update bindings by fixing dt_binding_check tool errors (update
On Thu, Sep 26, 2024 at 04:31:33PM GMT, Mahadevan wrote:
> Document the MDSS hardware found on the Qualcomm SA8775P platform.
>
> Signed-off-by: Mahadevan
> ---
>
> [v2]
> - Use fake DISPCC nodes to avoid clock dependencies in dt-bindings. [Dmitry]
> - Update bindings by fixing dt_binding_check
On Wed, Sep 25, 2024 at 02:49:48PM GMT, Abhinav Kumar wrote:
> On 9/25/2024 2:11 PM, Dmitry Baryshkov wrote:
> > On Wed, 25 Sept 2024 at 22:39, Jessica Zhang
> > wrote:
> > > On 9/24/2024 4:13 PM, Dmitry Baryshkov wrote:
> > > > On Tue, Sep 24, 2024 at
On Wed, 25 Sept 2024 at 23:28, wrote:
>
> On 2024-08-01 21:25, Dmitry Baryshkov wrote:
> > On Fri, Jun 28, 2024 at 04:39:38PM GMT, Barnabás Czémán wrote:
> >> This patch series add dpu support for MSM8996/MSM8953 devices.
> >>
> >> Note, by default these
On Wed, 25 Sept 2024 at 22:39, Jessica Zhang wrote:
>
>
>
> On 9/24/2024 4:13 PM, Dmitry Baryshkov wrote:
> > On Tue, Sep 24, 2024 at 03:59:21PM GMT, Jessica Zhang wrote:
> >> From: Dmitry Baryshkov
> >>
> >> All resource allocation is centered around
On Tue, Sep 24, 2024 at 05:14:49PM GMT, Jessica Zhang wrote:
>
>
> On 9/24/2024 4:41 PM, Dmitry Baryshkov wrote:
> > On Tue, Sep 24, 2024 at 03:59:32PM GMT, Jessica Zhang wrote:
> > > Cache the CWB block mask in the DPU virtual encoder and configure CWB
> > >
On Tue, Sep 24, 2024 at 05:05:43PM GMT, Abhinav Kumar wrote:
>
>
> On 9/24/2024 4:25 PM, Dmitry Baryshkov wrote:
> > On Tue, Sep 24, 2024 at 03:59:30PM GMT, Jessica Zhang wrote:
> > > If the clone mode enabled status is changing, a modeset needs to happen
> >
On Tue, Sep 24, 2024 at 05:37:30PM GMT, Jessica Zhang wrote:
>
>
> On 9/24/2024 4:16 PM, Dmitry Baryshkov wrote:
> > On Tue, Sep 24, 2024 at 03:59:22PM GMT, Jessica Zhang wrote:
> > > From: Dmitry Baryshkov
> > >
> > > Stop poking into CRTC state
gt; drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 2 ++
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 7 +--
> 3 files changed, 39 insertions(+), 2 deletions(-)
>
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
: Jessica Zhang
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 18 ++
> 1 file changed, 18 insertions(+)
>
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
On Tue, Sep 24, 2024 at 03:59:32PM GMT, Jessica Zhang wrote:
> Cache the CWB block mask in the DPU virtual encoder and configure CWB
> according to the CWB block mask within the writeback phys encoder
>
> Signed-off-by: Jessica Zhang
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 8
On Tue, Sep 24, 2024 at 03:59:31PM GMT, Jessica Zhang wrote:
> Add support for RM to reserve dedicated CWB pingpongs and CWB muxes
>
> For concurrent writeback, even-indexed CWB muxes must be assigned to
> even-indexed LMs and odd-indexed CWB muxes for odd-indexed LMs. The same
> even/odd rule app
On Tue, Sep 24, 2024 at 03:59:30PM GMT, Jessica Zhang wrote:
> If the clone mode enabled status is changing, a modeset needs to happen
> so that the resources can be reassigned
Sima's comment regarding crtc_state->mode_changed seems to be ignored...
>
> Signed-off-by: Jessica Zhang
> ---
> dri
On Tue, Sep 24, 2024 at 03:59:29PM GMT, Jessica Zhang wrote:
> Add the cwb_enabled flag to msm_display topology and adjust the toplogy
> to account for concurrent writeback
>
> Signed-off-by: Jessica Zhang
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 6 --
> drivers/gpu/drm/msm/disp/d
sm/disp/dpu1/dpu_rm.h | 2 ++
> 2 files changed, 17 insertions(+), 2 deletions(-)
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
m/disp/dpu1/dpu_hw_wb.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
| 1 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cwb.c | 73
> +
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cwb.h | 70 +++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 5 +-
> 4 files changed, 148 insertions(+), 1 deletion(
dpu_hw_mdss.h | 8
> 5 files changed, 14 insertions(+), 14 deletions(-)
>
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
g/dpu_10_0_sm8650.h | 21
> +
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 13 +
> 2 files changed, 34 insertions(+)
>
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
On Tue, Sep 24, 2024 at 03:59:22PM GMT, Jessica Zhang wrote:
> From: Dmitry Baryshkov
>
> Stop poking into CRTC state from dpu_encoder.c, fill CRTC HW resources
> from dpu_crtc_assign_resources().
>
> Signed-off-by: Dmitry Baryshkov
> [quic_abhin...@quicinc.com: cleaned up
On Tue, Sep 24, 2024 at 03:59:21PM GMT, Jessica Zhang wrote:
> From: Dmitry Baryshkov
>
> All resource allocation is centered around the LMs. Then other blocks
> (except DSCs) are allocated basing on the LMs that was selected, and LM
> powers up the CRTC rather than the encoder.
&
On Tue, Sep 24, 2024 at 03:59:17PM GMT, Jessica Zhang wrote:
> Add helper to check if the given CRTC state is in clone mode
>
> Signed-off-by: Jessica Zhang
> ---
> include/drm/drm_crtc.h | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git a/include/drm/drm_crtc.h b/include/drm/drm_cr
On Tue, 24 Sept 2024 at 14:31, Mahadevan P wrote:
>
>
> On 9/24/2024 5:46 PM, Dmitry Baryshkov wrote:
> > On Tue, Sep 24, 2024 at 04:42:02PM GMT, Mahadevan P wrote:
> >> On 9/12/2024 1:34 PM, Dmitry Baryshkov wrote:
> >>> On Thu, Sep 12, 2024 at 12:44:3
On Tue, Sep 24, 2024 at 04:42:02PM GMT, Mahadevan P wrote:
>
> On 9/12/2024 1:34 PM, Dmitry Baryshkov wrote:
> > On Thu, Sep 12, 2024 at 12:44:36PM GMT, Mahadevan wrote:
> > > Add definitions for the display hardware used on the
> > > Qualcomm SA8775P platfo
On Tue, 24 Sept 2024 at 09:16, Mahadevan P wrote:
>
>
> On 9/12/2024 1:26 PM, Dmitry Baryshkov wrote:
> > On Thu, Sep 12, 2024 at 12:44:32PM GMT, Mahadevan wrote:
> >> Add support for mdss and dpu driver on Qualcomm SA8775P platform.
> >>
> >> ---
&g
On Tue, 24 Sept 2024 at 09:36, Mahadevan P wrote:
>
>
> On 9/12/2024 1:30 PM, Dmitry Baryshkov wrote:
> > On Thu, Sep 12, 2024 at 12:44:37PM GMT, Mahadevan wrote:
> >> Add mdss and mdp DT nodes for SA8775P.
> >>
> >> Signed-off-by: Mahadevan
> >&g
On Mon, 23 Sept 2024 at 22:05, Akhil P Oommen wrote:
>
> On Wed, Sep 18, 2024 at 12:27:03AM +0300, Dmitry Baryshkov wrote:
> > On Wed, Sep 18, 2024 at 02:08:43AM GMT, Akhil P Oommen wrote:
> > > From: Puranam V G Tejaswi
> > >
> > > Add gpu an
S0 DPTX0 and DPTX1 have been conducted.
I'd prefer if there was a word 'only' in the last phrase, but I can live
without it.
Reviewed-by: Dmitry Baryshkov
>
> Signed-off-by: Soutrik Mukhopadhyay
> ---
> v2: No change
>
> v3: Fixed review comments from Konrad an
On Mon, Sep 23, 2024 at 05:01:48PM GMT, Soutrik Mukhopadhyay wrote:
> Add support for eDP PHY v5 found on the Qualcomm SA8775P platform.
>
> Reviewed-by: Dmitry Baryshkov
> Signed-off-by: Soutrik Mukhopadhyay
> ---
> v2: Fixed review comments from Dmitry
> - Reused
41 -
> 1 file changed, 17 insertions(+), 24 deletions(-)
>
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
On Sun, Sep 22, 2024 at 12:14:48AM GMT, Dmitry Baryshkov wrote:
> The pll_cmp_to_fdata() was never used by the working code. Drop it to
> prevent warnings with W=1 and clang.
>
> Reported-by: Jani Nikula
> Closes:
> https://lore.ke
ect prefix to "drm/msm: ".
> * Added Fixes tag.
> v1:
> https://lore.kernel.org/all/pd76zf55h3kjpmgiydiu4br35bwlzsey2losublklv4o4ta7ko@z3gzy2eec5qh/
>
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
The pll_cmp_to_fdata() was never used by the working code. Drop it to
prevent warnings with W=1 and clang.
Reported-by: Jani Nikula
Closes:
https://lore.kernel.org/dri-devel/3553b1db35665e6ff08592e35eb438a574d1ad65.1725962479.git.jani.nik...@intel.com
Signed-off-by: Dmitry Baryshkov
On Thu, 12 Sep 2024 16:30:15 +0800, Jinjie Ruan wrote:
> As commit cbe16f35bee6 ("genirq: Add IRQF_NO_AUTOEN for request_irq/nmi()")
> said, reqeust_irq() and then disable_irq() is unsafe. In the small time gap
> between request_irq() and disable_irq(), interrupts can still come.
>
> IRQF_NO_AUTOE
On Sat, 21 Sept 2024 at 20:23, Krzysztof Kozlowski wrote:
>
> On 12/09/2024 09:14, Mahadevan wrote:
> >
> > +clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
> > + <&gcc GCC_DISP_HF_AXI_CLK>,
> > + <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>;
> > +
> > +inter
Rather than hand-coding UBWC_STATIC value calculation, define
corresponding bitfields and use them to setup the register value.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_mdss.c | 36 +++---
drivers/gpu/drm/msm/msm_mdss.h | 3
Follow other msm_mdss_setup_ubwc_dec_nn functions and use individual
bits instead of just specifying the value to be programmed to the
UBWC_STATIC register.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_mdss.c | 17 +
drivers/gpu/drm/msm/msm_mdss.h | 1 -
2 files
Move existing register definitions to mdss.xml and use generated defines
for registers access instead of hand-coding everything in the source
file.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_mdss.c | 35 +++---
drivers/gpu/drm/msm/registers
In preparation of adding more registers, move MDSS-related headers to
the separate top-level file.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/Makefile | 1 +
drivers/gpu/drm/msm/registers/display/mdp5.xml | 16
drivers/gpu/drm/msm/registers
o not document the actual purpose. Hopefully comparing this data with
the more documented Adreno UBWC feature bits will provide information
about the meaning of those bits.
Signed-off-by: Dmitry Baryshkov
---
Dmitry Baryshkov (4):
drm/msm: move MDSS registers to separate header file
d
gt; unnecessary and can lead to confusion in the code structure.
>
> Reported-by: Abaci Robot
> Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=9852
> Signed-off-by: Yang Li
> ---
> drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c | 2 +-
> 1 file changed, 1 insertion(+), 1
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31211
>
> To: Rob Clark
> To: Sean Paul
> To: Konrad Dybcio
> To: Abhinav Kumar
> To: Dmitry Baryshkov
> To: Marijn Suijten
> To: David Airlie
> To: Daniel Vetter
> To: Maarten Lankhorst
> To: Maxime Ripa
On Wed, Sep 18, 2024 at 02:08:41AM GMT, Akhil P Oommen wrote:
> From: Puranam V G Tejaswi
>
> Add support for Adreno 663 found on sa8775p based platforms.
>
> Signed-off-by: Puranam V G Tejaswi
> Signed-off-by: Akhil P Oommen
> ---
> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 19
On Wed, Sep 18, 2024 at 02:08:43AM GMT, Akhil P Oommen wrote:
> From: Puranam V G Tejaswi
>
> Add gpu and gmu nodes for sa8775p based platforms.
Which platforms? The commit adds nodes to the SoC and the single RIDE
platform.
>
> Signed-off-by: Puranam V G Tejaswi
> Signed-off-by: Akhil P Oomm
On Tue, 17 Sept 2024 at 10:40, Soutrik Mukhopadhyay
wrote:
>
>
> On 9/13/2024 5:12 PM, Dmitry Baryshkov wrote:
> > On Fri, 13 Sept 2024 at 13:38, Soutrik Mukhopadhyay
> > wrote:
> >> In order to support different HW versions, introduce aux_cfg array
> >>
On Mon, Sep 16, 2024 at 06:04:08PM GMT, Abhinav Kumar wrote:
>
>
> On 9/2/2024 8:22 PM, Dmitry Baryshkov wrote:
> > Historically CRTC resources (LMs and CTLs) were assigned in
> > dpu_crtc_atomic_begin(). The commit 9222cdd27e82 ("drm/msm/dpu: move hw
> > resource
On Mon, Sep 16, 2024 at 05:23:55PM GMT, Krzysztof Kozlowski wrote:
> On Fri, Sep 13, 2024 at 04:07:51PM +0530, Soutrik Mukhopadhyay wrote:
> > Add compatible string for the supported eDP PHY on sa8775p platform.
> >
> > Signed-off-by: Soutrik Mukhopadhyay
> > ---
> > v2: No change
> >
>
> Acke
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